Abstract-This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-m CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches.Index Terms-CMOS digital integrated circuits, CMOS memory circuits, digital integrated circuits, integrated logic circuits, multivalued logic circuits.
A W-band, tapered constructive wave power amplifier (TCWPA) has been designed and fabricated in a 0.12 µm SiGe BiCMOS technology. The amplifier has a 3 dB BW of 19 GHz from 91-110 GHz and a maximum gain of 12.5 dB at 101 GHz. At 98 GHz, OP 1dB is 4.9 dBm. At 97 GHz, Psat is 5.9 dBm and the PAE is 7.2%. The amplifier operates from a 2.4 V supply and occupies an area of 0.22 mm 2 .
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