Algorithmic and architectural transformations for low power realization of FIR filters

Mehendale, H.; Sherlekar, S.D.; Venkatesh, G.

doi:10.1109/icvd.1998.646571

Cited by 16 publications

(16 citation statements)

References 16 publications

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“…Thus, the filter output is independent of the order of computing the coefficient product [8]. Coefficient ordering is used in [8] as a technique for low power, where all coefficients are ordered in a Fully-Sequential circuit so as to minimize the transitions in the multiplier input and bus.…”

Section: B Coefficient Manipulationmentioning

confidence: 99%

“…For the hardwired implementation, architectural transformations have targeted performance, power and computational complexity [8]. A very efficient technique when targeting low power consumption is to reduce the supply voltage, resulting in a power reduction proportional to the square of the reduction in the supply voltage.…”

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

“…Thus, some techniques called Coefficient Ordering, Selective Coefficient Negation and Coefficient Scaling have addressed the use of coefficient manipulation in order to reduce the switching activity in the multipliers inputs [1], [8]. The main goal of these techniques is to minimize the Hamming distance between consecutive coefficients in order to reduce power consumption in the multiplier input and data bus.…”

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

“…For applications where the flexibility of the programmable processor is not required, a hardwired implementation is the preferred choice as such an implementation typically results in higher throughput and lower power [8].…”

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

“…Additionally, we propose an extension to the Coefficient Ordering technique [8] that aims at reducing the power dissipation by optimizing the ordering of the coefficient-data product computation. We have used this technique in the FIR and FFT implementations.…”

Section: Introductionmentioning

confidence: 99%

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Low power architectures for FFT and FIR dedicated datapaths

Costa

Bampi²,

Monteiro³

2003 46th Midwest Symposium on Circuits and Systems

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This paper addresses the use of architectural transformations for the low power realization of FIR filter and FFT algorithms on dedicated datapath architectures. We report significant power savings using the propose methodology. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2's complement is a widely used encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. This architecture uses radix-2 m encoding, which leads to a reduction of the number of partial lines, enabling large gains in performance and power consumption. The proposed architecture is applied to the DSP architectures and compared with the state of the art. Due to the characteristics of the FIR filter and FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations in order to minimize the power consumption in the implemented architectures is also investigated.

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Section: B Coefficient Manipulationmentioning

confidence: 99%

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

Section: Related Work On Dsp Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low power architectures for FFT and FIR dedicated datapaths

Costa

Bampi²,

Monteiro³

2003 46th Midwest Symposium on Circuits and Systems

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Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths

Costa

Monteiro²,

Bampi

2006

IFIP International Federation for Information Processing

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Abstract:This paper addresses the use of low power techniques applied to FIR filter and FFT dedicated datapath architectures. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2's complement is the most common encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. This architecture uses radix-2'" encoding, which leads to a reduction of the number of partial lines. Each group of m bits uses the Gray code, thus potentially further reducing the switching activity both internally and at the inputs. The multiplier architecture is applied to the DSP architectures and compared with the state of the art. Due to the characteristics of the FIR filter and FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations in order to minimize the power consumption in the implemented architectures is also investigated. As will be shown, the use of the low power operators with an appropriate choice of coefficients can contribute for the reduction of power consumption of the FIR and FFT architectures. Additionally, a new algorithm for the partitioning and ordering of the coefficients is presented. This technique is experimented in a Semi-Parallel architecture which enables speedup transformation techniques.

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