Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths

Abstract

Abstract:This paper addresses the use of low power techniques applied to FIR filter and FFT dedicated datapath architectures. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2's complement is the most common encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. This architecture uses radix-2'" encoding, which leads to a reduction of the number of partial lines. Each group of m bits uses the Gray code, thus potentially further reducing the switching activity both internally and at the inputs. The multiplier architecture is applied to the DSP architectures and compared with the state of the art. Due to the characteristics of the FIR filter and FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations in order to minimize the power consumption in the implemented architectures is also investigated. As will be shown, the use of the low power operators with an appropriate choice of coefficients can contribute for the reduction of power consumption of the FIR and FFT architectures. Additionally, a new algorithm for the partitioning and ordering of the coefficients is presented. This technique is experimented in a Semi-Parallel architecture which enables speedup transformation techniques.

Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization

“…An extension of the technique of [7] was experimented in [4] in a semi-parallel architecture, where the hardware is duplicated and coefficients are partitioned into groups of coefficients. Thus, the problem is related to finding the best partition for each coefficient by calculating the minimum Hamming distance between the coefficients into each group.…”

“…Thus, the problem is related to finding the best partition for each coefficient by calculating the minimum Hamming distance between the coefficients into each group. In the algorithm presented by [4], the cost function is calculated for all the combinations over the coefficients. As the number of taps was small (eight) the number of permutations was still reasonable.…”

“…Thus, coefficient ordering has been used as a technique for low power, where all coefficients are ordered in a Fully-Sequential circuit to minimize the transitions in the multiplier input and data bus [3]. In [4], this technique was extended-up by using the ordering and partitioning of the coefficients for the Semi-Parallel FIR filter architecture, where the hardware is duplicated and coefficients are partitioned into groups of coefficients. Thus, the problem in both cases is related to finding the best partition for each coefficient by calculating the minimum Hamming distance between the coefficients into each group.…”

“…Although these techniques, presented in [3] and [4], can optimize the partitioning and ordering of the coefficients, the cost function of the algorithms is calculated for all the combinations over the coefficients, which is limited to a small group of coefficients, where the total number of permutations is calculated in a still reasonable time. However, for a larger number of coefficients, these exhaustive algorithms are less attractive due to the time required to process a higher number of combinations.…”

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“…Also, a study of methods for power reduction applied to the FFT computation process could be performed. In [51] and [52], methods for reducing switching activity in the data bus of FFT and similar algorithms are shown.…”