Low power architectures for FFT and FIR dedicated datapaths

Abstract

This paper addresses the use of architectural transformations for the low power realization of FIR filter and FFT algorithms on dedicated datapath architectures. We report significant power savings using the propose methodology. New low power arithmetic operators are used as basic modules. In FIR filter and FFT algorithms, 2's complement is a widely used encoding for signed operands. We use a new architecture for signed multiplication, which maintains the pure form of an array multiplier. This architecture uses radix-2 m encoding, which leads to a reduction of the number of partial lines, enabling large gains in performance and power consumption. The proposed architecture is applied to the DSP architectures and compared with the state of the art. Due to the characteristics of the FIR filter and FFT algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering of these operations in order to minimize the power consumption in the implemented architectures is also investigated.

Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs

“…Depending on the type of architecture: parallel, burst I/O etc., the storage space will be configured at the input point. The various data format such as canonical signed digit(CSD), minimal signed digit(MSD), or Logarithmic data representation adopted in case of precise data path unit such as FIR filter reported in [10], however a straight forward data format representation is considered in this work in view of observing the artefact such as s creating numerical noise as a result of round-up and round-down approximations (i.e. finite word length effects) during hardware FFT implementation, computation, and analysis.…”