Algorithm and architecture for logarithm, exponential, and powering computation

Pineiro, J.-A.; Ercegovac, M.D.; Bruguera, J.D.

doi:10.1109/tc.2004.53

Cited by 83 publications

(60 citation statements)

References 21 publications

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“…However, this work is very application-specific. A more generic implementation is presented in Pineiro et al [2004]. It is also based on (1), where exponential and logarithm are evaluated by high-radix iterative algorithms using redundant number representations.…”

Section: Previous Workmentioning

confidence: 99%

“…They can be used to implement complex applications, including floating-point ones [Scrofano et al 2008;Underwood 2004;Woods and VanCourt 2008;Zhuo and Prasanna 2008]. This has sparked the development of floating-point units targeting FPGAs, first for the basic operators mimicking thoses found in microprocessors [Belanovic and Leeser 2002;Louca et al 1996;Shirazi et al 1995], then more recently for operators which are more FPGA-specific, for instance accumulators [Bodnar et al 2006;de Dinechin et al 2008;Luo and Martonosi 2000;Wang et al 2006] or elementary functions Doss and Riley 2004;Pineiro et al 2004].…”

Section: Introduction 1floating Point Acceleration Using Fpgasmentioning

confidence: 99%

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Floating-Point Exponentiation Units for Reconfigurable Computing

Dinechin

Echeverría

López‐Vallejo

et al. 2013

ACM Trans. Reconfigurable Technol. Syst.

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The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x y as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floatingpoint multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

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Section: Previous Workmentioning

confidence: 99%

Section: Introduction 1floating Point Acceleration Using Fpgasmentioning

confidence: 99%

Floating-Point Exponentiation Units for Reconfigurable Computing

Dinechin

Echeverría

López‐Vallejo

et al. 2013

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

“…However, in our channel model generator this transformation is not explicitly required since we can incorporate this constant, log 2 (10), into the channel model parameters which are pre-computed and stored as constants in the ROM. A digital recurrence method is the primary approach used for implementations of hardware powering [13]. However, it exhibits the typical trade-off between the number of iterations and the size of the radix that is common to all digit recurrence algorithms.…”

Section: Gaussian Noise Random Number Generatormentioning

confidence: 99%

Hardware channel model for ultra wideband systems

Kan

Sobelman

2006

2006 IEEE International Conference on Field Programmable Technology

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Abstract-We present a digital hardware model for ultra wideband channels. The system runs at 80 MHz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The design flow is based on Matlab Simulink as the model builder, followed by Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.

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“…T HE generation of elementary functions such as log() and antilog() finds uses in many areas such as digital signal processing (DSP), 3-D computer graphics, scientific computing, artificial neural networks, logarithmic number systems (LNS), and other multimedia applications [1]. Our approach provides a good solution for field-programmable gate array (FPGA)-based applications that require high accuracy with a low cost in terms of required lookup table (LUT) size.…”

Section: Introductionmentioning

confidence: 99%

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

Paul

Jayakumar

Khatri

2009

IEEE Trans. VLSI Syst.

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Abstract-The realization of functions such as log() and antilog() in hardware is of considerable relevance, due to their importance in several computing applications. In this paper, we present an approach to compute log() and antilog() in hardware. Our approach is based on a table lookup, followed by an interpolation step. The interpolation step is implemented in combinational logic, in a fieldprogrammable gate array (FPGA), resulting in an area-efficient, fast design. The novelty of our approach lies in the fact that we perform interpolation efficiently, without the need to perform multiplication or division, and our method performs both the log() and antilog() operation using the same hardware architecture. We compare our work with existing methods, and show that our approach results in significantly lower memory resource utilization, for the same approximation errors. Also our method scales very well with an increase in the required accuracy, compared to existing techniques.Index Terms-Field-programmable gate arrays (FPGAs), floating point arithmetic, logarithmic arithmetic, VLSI.

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Algorithm and architecture for logarithm, exponential, and powering computation

Cited by 83 publications

References 21 publications

Floating-Point Exponentiation Units for Reconfigurable Computing

Floating-Point Exponentiation Units for Reconfigurable Computing

Hardware channel model for ultra wideband systems

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

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