Air-Stable P-Doping in Record High-Performance Monolayer WSe<sub>2</sub> Devices

Chiang, Chin‐Cheng; Lan, Hao-Yu; Pang, Chin‐Sheng; Appenzeller, Joerg; Chen, Zhihong

doi:10.1109/led.2021.3135312

Cited by 38 publications

(24 citation statements)

References 18 publications

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“…Also, R c = 2.1–4.5 kΩ (or contact resistivity of 30.2–64.8 kΩ μm) corresponding to n = 1.5 × 10 12 cm –2 is comparable to Co/hBN tunneling contact in monolayer MoS 2. Low R c values in 1L-WSe 2 FETs have been reported in previous studies; − however, those devices do not exhibit Ohmic contact behavior at cryogenic temperatures, and the contact resistivity at low carrier densities needs further investigation. In contrast to other reports, the contact resistivity in our work remains reasonably low even at very low carrier density near the threshold .…”

Section: Resultsmentioning

confidence: 80%

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃

Chen

Xing

Liu

et al. 2022

ACS Appl. Electron. Mater.

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Monolayer tungsten diselenide (1L-WSe2) has been widely used for studying emergent physics due to the unique properties of its valence bands. However, electrical transport studies have been impeded by the lack of a reliable method to realize Ohmic hole-conducting contacts to 1L-WSe2 especially at low carrier densities and low temperatures. Here, we report low-temperature p-type Ohmic contact to 1L-WSe2 field-effect transistors at carrier densities (n) below n = 1 × 1012 cm–2 with negligible temperature dependence down to the lowest measured temperature (10 K). The non-rectifying barrier is achieved between 1L-WSe2 and molybdenum trioxide (MoO3), where 1L-WSe2 underneath MoO3 is heavily hole-doped through surface transfer doping. Electrical transport measurements reveal linear current–voltage relations at a temperature of 10 K and carrier densities from n = 7.7 × 1011 cm–2 to below the threshold. The finding is also supported by nearly temperature-independent output curves up to room temperature and a negligible contact barrier down to the subthreshold regime. Furthermore, the contact resistivity of MoO3-contacted 1L-WSe2 FET is 30.2–64.8 kΩ μm at n = 1.5 × 1012 cm–2, which is the lowest reported for 1L-WSe2 FETs at such low carrier density. Realizing robust p-type Ohmic contact to a 2D transition metal dichalcogenide semiconductor will enable direct electronic measurements of quantum transport in correlated phases in the valence bands of monolayer semiconductors.

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Section: Resultsmentioning

confidence: 80%

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃

Chen

Xing

Liu

et al. 2022

ACS Appl. Electron. Mater.

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“…Stacked designs require either a reduction of the MOCVD growth temperature for high quality 2D films or a homogeneous transfer process which can deliver the necessary yield on an industrial scale [ 109 ]. In addition, despite low contact resistances having been achieved for n-type MoS

FETs, contact resistances for p-type FETs still exceed the target value by one order of magnitude [ 66 ] and scaled contact lengths are challenging. Finally, one of the major obstacles for 2D CMOS is the identification of a suitable gate insulator.…”

Section: Discussionmentioning

confidence: 99%

“…Thus, while two promising candidates for Ohmic contacts to n-type semiconductors have been identified with Bi and Sb, there are yet few demonstrations of low-resistive contacts to p-type devices. Recently, good results have been achieved for nitric oxide doped WSe

FETs with a resistance of 950

m [ 66 ] or Ru contacts to WSe

FETs with a resistance of

m [ 30 ].…”

Section: Contact Engineeringmentioning

confidence: 99%

“…In general, substitutional doping in 2D materials has been realized by replacing both the cationic components (e.g., replace Mo with Nb in MoS

) [ 94 ] and the anionic components (e.g., replace S with N in WS

) [ 66 , 95 ] of TMDs [ 48 ]. However, substitutional doping schemes in 2D materials typically lead to severe lattice defects in the 2D layer and poor dopant activation despite structural incorporation of dopants [ 28 ].…”

Section: Cmos Process Integrationmentioning

confidence: 99%

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Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials

Knobloch

Selberherr

2022

Nanomaterials

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For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.

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“…it becomes apparent that high contact resistance (R C ) is one of their major drawbacks [1], [2], [3]. Much effort has recently been invested to lower R C to 2-D semiconductors by increasing their charge carrier concentration (n) or by depinning the Fermi level at the metal/semiconductor interface [4], [5], [6], [7], [8], [9], [10], [11], [12]. However, the calculations of the intrinsic lower limit of contact resistivity to bulk semiconductors showed that the number of states available for carrier transport determines R C at the extreme end of scaling [13], [14].…”

mentioning

confidence: 99%

High Number of Transport Modes: A Requirement for Contact Resistance Reduction to Atomically Thin Semiconductors

Ber

Grady

Pop

et al. 2023

IEEE Trans. Electron Devices

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Electrical contacts to atomically thin 2-D semiconductors are considered as the hindering aspect of electronic devices based on these materials. The high resistance of such contacts stems from their Schottky nature in contrast to the desired low-resistance Ohmic contacts. This issue of Schottky contacts is thus one of the major inhibitors to the integration of 2-D materials into mainstream technology. In this work, we explore contact resistance (R C ) to atomically thin 2-D semiconductors in terms of the injected current through the Schottky barrier (SB) by using the Landauer−Büttiker formalism as well as experimental measurements and technology computer aided design (TCAD) simulations. We show that the SB height and width, which are determined by the metalsemiconductor interface and the number of charge carriers in the semiconductor channel, respectively, affect R C when it is relatively high (R C > 1 k •µm). However, the number of transport modes for carrier injection is the limiting factor for aggressive R C lowering (R C < 1 k •µm), even for nearzero SB height. Our results show that to reduce R C below 100 •µm, large number of transport modes are required, which can be accomplished through raising the number of channel carriers above 5•10 13 cm −2 by means of heavy doping or gating. Our conclusions offer insight for future contact engineering and can explain recently published state-of-the-art results.

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Air-Stable P-Doping in Record High-Performance Monolayer WSe₂ Devices

Cited by 38 publications

References 18 publications

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials

High Number of Transport Modes: A Requirement for Contact Resistance Reduction to Atomically Thin Semiconductors

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Air-Stable P-Doping in Record High-Performance Monolayer WSe2 Devices

Cited by 38 publications

References 18 publications

P-Type Ohmic Contact to Monolayer WSe2 Field-Effect Transistors Using High-Electron Affinity Amorphous MoO3

P-Type Ohmic Contact to Monolayer WSe2 Field-Effect Transistors Using High-Electron Affinity Amorphous MoO3

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials

High Number of Transport Modes: A Requirement for Contact Resistance Reduction to Atomically Thin Semiconductors

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Product

Resources

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Air-Stable P-Doping in Record High-Performance Monolayer WSe₂ Devices

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃

P-Type Ohmic Contact to Monolayer WSe₂ Field-Effect Transistors Using High-Electron Affinity Amorphous MoO₃