Aging-based leakage energy reduction in FPGAs

Abstract

The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.

Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization

“…In the last decade, power gating was recognized as an effective way to reduce leakage energy [21] [22][23] [24][25] [35]. Our goal is to provide an impetus for further development of this line of optimization by showing how a simple but rich power gating structure can be adaptively used to facilitate energy minimization in modern and pending systems.…”

Gate sizing in the presence of gate switching activity and input vector control

“…The technique is further combined with circuit aging in preand-post silicon phases. [13] [20]. IVC has also been explored in the presence of uncertainty [14].…”