Gate sizing in the presence of gate switching activity and input vector control

Abstract

Abstract-We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we interchangeably conduct gate sizing and refining the IVC. As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. We evaluate our approach on standard benchmarks in 45 nm technology, showing promising improvement, achieving up to 62% (29% avg.) energy savings compared to the traditional objective function.

Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization

“…Two main reasons are that feature scaling drastically reduced not just supply and threshold voltages but also their gap. Also, process variation causes threshold voltage to become subject to a relatively wide distribution, and the threshold voltage must be higher than the highest threshold voltage of any transistor [7][12] [14]. Therefore, although dynamic voltage scaling is still important, power gating may now enable much better improvements.…”

A temperature-aware synthesis approach for simultaneous delay and leakage optimization

“…The gate width is adjusted to achieve various drive strengths, enabling circuit power and timing trade-offs. In the discrete domain, gate sizing is an NP-Hard problem [5] and several well known solutions have been proposed, such as Lagrangian relaxation [20], dynamic programming [2], combinatorial relaxation [9], and sensitivity-based optimizations [3][4] [7][21]. Dual threshold voltage (V t ) combined with gate sizing has also been proposed [8].…”

“…The cost for acquiring accurate delay values of the entire circuit is significantly reduced, while minimally impacting accuracy. To further improve runtimes at the expense of accuracy, groups of gates may be sized at a time as done in [3] [7].…”

Maximizing yield in Near-Threshold Computing under the presence of process variation

“…However, only leakage power is accounted with no PV model assumed. Additional improvements when accurate operating conditions such as temperature, gate switching, and input vector state leakage computations are accounted for [31][32], however, PV is not considered in their models as well.…”