Ageing and thermal recovery of advanced SiGe heterojunction bipolar transistors under long-term mixed-mode and reverse stress conditions

A Physics-Based Circuit Aging Model for Mixed-Mode Degradation in SiGe HBTs

“…For long stress periods, the approximate solution to the R-D model given by (6) is not valid as the interface trap density saturates to N 0 . This phenomena has been explored in [11] and [13] and modeled using a time varying aging rate. For the particular technology used in this paper, the deviation of the time exponent n was not seen until base current changed by several orders of magnitude.…”

“…Similar approaches have been made in the past with some success, such as for hot carrier breakdown of CMOS devices [7], [8]; however, most models fail to present the full picture for circuit aging, either through the use of simple physical models or incomplete representation of aging effects in the device [9]- [11]. Effective empirical aging models, such as in [12] and [13], have been developed, but they represent a nonideal solution, as they fail to provide an intuitive look at the causes of the aging and may not be as adaptable across different technologies. This paper embodies the first steps in the development of a physics-based damage model as a wrapper for silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) compact models that will cover the major components of hot carrier degradation.…”

Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges

“…Indeed, a high bias condition beyond the SOA edges leads to the base current degradation. Although, a recovery, due to traps annealing, of the degradation can be observed at high junction temperature [7] meaning that the hot-carrier degradation depends on both avalanche and self-heating effects.…”

5. Reliability

“…Differently from MOSFETs, the collector current remains unaffected, and therefore it can in principle be stated that HC degradation is less critical in bipolar transistors, including the SiGe HBT technology; however, it still entails a number of undesirable consequences, such as current gain reduction (due to the base current growth), noise figure increase, shift of the bias point outside of the functional range, as well as increased power consumption in power amplifiers [Ven00,Cre04,Che09]. Such effects have been traditionally studied under reverse base-emitter stress conditions, where HCs are created by large electric fields across the base-emitter junction (see the early papers [Bur88,Gog00] and the more recent [Sas14a,Sas14b,Fis15]); this stress test was indeed considered as appropriate for assessing device reliability in BiCMOS operation [Bur88].…”

“…Another stress technique has been subsequently proposed and quickly accepted in the literature, which is more representative of device degradation in practical mixed-signal and RF circuit applications; in this technique, referred to as mixed mode (MM) [Zha02], the device under test (DUT) is usually operated in common-base (CB) configuration while being simultaneously subjected to large emitter current density (J E,stress ) and collector-base voltage (V CB,stress ) [the corresponding V CE being higher than the openbase breakdown voltage (BV CEO )] [Zhu05,Dio08,Cha15]. Although this biasing condition may seem too severe, the instantaneous operating point of a transistor (e.g., in oscillators and in noise/power amplifiers) can reach either high voltage or high current under large-signal operating mode, thereby gradually increasing HC-triggered damage [Che09,Fis08,Gre09,Fis15]. The high -and continuously applied -stress conditions J E,stress and V CB,stress are also denoted as accelerating factors, since they give rise to significant MM stress degradation in a relatively short time.…”