Advanced yield enhancement methodology for SoCs

Abstract

A yield simulator utilizing the erfracted critical area and a SoC yield management system has been developed. This system drastically improved accuracy of SoC yield prediction and successfilly extracted the critical areas of all layers of 0.I8pnSoCs in approximately one hour. For yieldprediction, we have thus far extracted critical areas of over I50 SoCs since the 0.I8pn nodes. and performed analysis ofyield-loss factors.There me two factors that aflect the device yield: field defects and product-inherent parametric failure. The yield calculated on the basis of critical areas is a prediction derived considering only field defects. It has been confirmed that SoCs failed to achieve the prediction had product-inherent parametric problems.The new system allows us to determine early in the development cycle whether or not a SoC has any inherent problems. The new system helps to quickly identifv the root cause of a yield loss and reduce the time required to obtain yield improvement.Based on the experience of analyzing many SoC products, we have acquired design-for-manufachrring (DFM) expertise for improving yieldr for new and next-generation products.

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

“…Thus, with 80% of the product being discarded, newer and faster schemes should be developed for detection and correction of these faults. To achieve increased yields various methods are adopted like modifying layout shapes, design rules, conditions of processes [2,3] etc. Yield ramp up thus becomes very crucial for production control, operation planning, material management and timely product delivery.…”