Short Critical Area Computational Method Using Mathematical Morphology

Wang, Junping; Hao, Yue

doi:10.1007/11596981_116

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2012

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“…With the increase in integrated circuit(IC) complexity and chip area, the decrease in the size of features and gate oxide thickness, and the widely use of sub-wavelength lithography [1,2], the reduction of the IC yield does further aggravate the competition in the market and the quality of the semiconductor products [3,4]. Therefore it is very significant to study how to reasonably adjust the layout to improve the yield of IC.…”

Section: Introductionmentioning

confidence: 99%

COE Based on Redundancy Material Defect

Wang

Pan

Pang

et al. 2012

AMR

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In the nanometer technology node, the contradiction between high investment and low yield has got more and more prominent, so it plays a very significant role in improving the yield to optimize layout. The COE, Critical area On Edge network, which is a kind of network based on the redundancy material defect with edges expressing critical areas, is constructed in this paper. Vertexes stand for nets of the layout, and edges do short circuit areas existing in nets. By studying the applications of COE in DFM, it is indicated that the COE provides a new way to the research of nanometer node in DFM.

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Section: Introductionmentioning

confidence: 99%