The traveling salesman problem (TSP) is one of the most important problems in combinational optimization. Many works have done for this problem using Ant Colony Optimization (ACO). The ACO is one of the most powerful optimization methods that combines distributed computation, auto-catalysis (positive feedback) and constructive greedy heuristic in finding optimal solutions for combinational optimization problems. Most of these previous works deal with software processing. However, ACO has the inherent problem of requiring substantial processing time. Therefore, the dedicated ACO hardware becomes important when applying ACO to combinational problems. In this paper, we propose a new hardware architecture for ACO. No previous studies have, to our knowledge, applied ACO hardware to TSP, as this study does using the proposed architecture. Experimental results to evaluate the proposed algorithm show improvement comparison with software processing.
This paper outlines the concepts and the key technologies of design automation for developing high-performance microprocessor chips. The goals of the design automation system are twofold: (1) reducing the development period, (2) implementing high performance.Problems in design automation include concurrent verification of both logic and timing design, incremental physical design, and a cooperative timing-driven placement and a routing procedure which accept various designer's specifications. Solutions to these problems are presented.
This paper discusses the optimal placement technique for LSI cells through genetic algorithms, and focuses particularly on the following points: (1) The algorithm has a two-level hierarchical structure consisting of "outline placement", which partitions an LSI chip area into several areas, and "detail placement", which determines cell positions in the partitioned area.The procedure for determining optimal cell positions is then explained. (2) For selection control, which is one of the genetic operations, new objective functions are introduced at each phase in addition to the usual objective function based on total virtual wire length. The objective function for outline placement controls dispersing wire congestion and that for detail placement controls eliminating local wire congestion. (3) Parallel processing systems suited to both outline placement and detail placement are studied. The experimental results prove that the proposed algorithm is effective for reducing local wire congestion on a chip, as well as total virtual wire length, and increasing the processing speed while preventing the deterioration of solutions.
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