Advanced wafer bonding solutions for TSV integration with thin wafers

Kim, Bioh; Matthias, Thorsten; Wimplinger, Markus; Lindner, Paul

doi:10.1109/3dic.2009.5306551

Cited by 11 publications

(5 citation statements)

References 3 publications

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“…Not only can it shorten wires with smaller chip sizes, but also it is a new technology platform for heterogeneous integration by stacking and connecting dissimilar materials or different modules on one substrate. Today, the prebonding wafer-to-wafer alignment accuracy can be achieved on the order of 0.25 μm using commercially available wafer-to-wafer alignment tools [5,6] . However, the process related misalignment has yet to be thoroughly studied, while it becomes more significant.…”

Section: X-tackingmentioning

confidence: 99%

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Zhang¹,

Xu²,

Wang³

et al. 2019

Journal of Microelectronic Manufacturing

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3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a three-dimensional vertical structure with high-aspect ratio. Obviously top-down images is not enough for process control, instead inner structure control becomes much more important than before, e.g. channel hole profiles. Besides, multi-layers, special materials and YMTC unique X-Tacking technology also bring other metrology challenges: high wafer bow, stress induced overlay, opaque film measurement. Technical development can adopt some destructive methodology (TEM, etch-back SEM), while manufacturing can only use nondestructive method. These drive some new metrology development, including X-Ray, mass measure and Mid-IR spectroscopy. As 3D NAND suppliers move to >150 layers devices, the existing metrology tools will be pushed to the limits. Still, the metrology must innovate.

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Section: X-tackingmentioning

confidence: 99%

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Zhang¹,

Xu²,

Wang³

et al. 2019

Journal of Microelectronic Manufacturing

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show abstract

“…In this laser-beam-assisted method, although the relative position of the layers could be determined, it was difficult to align the absolute position of the layers because of the periodic appearance of the same diffraction patterns. In addition, the diffraction patterns became complex when multilayered structures were aligned and stacked [34]. Subsequently, we employed a method using vernier-caliper markers [35] to obtain the absolute value of misalignment.…”

Section: Misalignment Detection By Image Recognition Techniquementioning

confidence: 99%

“…In addition, the diffraction patterns became complex when multilayered structures were aligned and stacked [34]. Subsequently, we employed a method using vernier-caliper markers [35] to obtain the absolute value of misalignment.…”

Section: Misalignment Detection By Image Recognition Techniquementioning

confidence: 99%

Fabrication of 3D Photonic Crystals toward Arbitrary Manipulation of Photons in Three Dimensions

2016

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Abstract:The creation of large-area, unintentional-defect-free three-dimensional (3D) photonic crystals in the optical regime is a key challenge toward the realization of the arbitrary 3D manipulation of photons. In this article, we discuss an advanced fabrication method of 3D silicon photonic crystals based on the highly accurate alignment and wafer bonding of silicon-on-insulator (SOI) wafers. We introduce an advanced alignment system, in which the alignment process is automated by image recognition and feed-back control of stages, and show that it achieves an alignment accuracy better than~50 nm. The bonding of SOI wafers is also investigated to obtain 3D crystals composed of highly pure crystalline silicon. We show the fabrication results of large-area 3D photonic crystals based on such considerations and demonstrate the successful introduction of artificial defects as functional components, such as coupled waveguide pairs or waveguides/nanocavities. We expect that these will be pioneering results toward the arbitrary 3D control of photons using 3D photonic crystals.

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“…developing capped fluid channels and cantilever beams. Besides, wafer bonding is an imperative process for the through silicon via (TSV) technologies in IC stacks, such as temporary bonding for carriers and permanent bonding for interposers [2]. During the past few decades, plenty of wafer bonding methods have been studied and reported [3,4].…”

Section: Introductionmentioning

confidence: 99%

The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

Liang

Liu

et al. 2017

J. Micromech. Microeng.

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KOH etching and Au/Si eutectic bonding are cost-efficient technologies for 3D device fabrication. Aimed at investigating the process compatibility of KOH etching and Au/Si bonding, KOH etching tests have been carried out for Au/bulk Si and Au/amorphous Si (a-Si) bonding wafers in this paper. For the Au/bulk Si bonding wafer, a serious underetch phenomenon occurring on the damage layer in KOH etching definitely results in packaging failure. In the microstructure analysis, it is found that the formation of the damage layer between the bonded layer and bulk Si is attributed to the destruction of crystal Si lattices in Au/bulk Si eutectic reaction. Considering the occurrence of underetch for Au/Si bonding must meet two requirements: the superfluous Si and the defective layer near the bonded layer, the Au/a-Si bonding by regulating the a-Si/Au thickness ratio is presented in this study. Only when the a-Si/Au thickness ratio is relatively low are there not underetch phenomena, of which the reason is the full reaction of the a-Si layer avoiding the formation of the damage layer for easy underetch. Obviously, the Au/a-Si bonding via choosing a moderate a-Si/Au thickness ratio (⩽1.5:1 is suggested) could be reliably compatible with KOH etching, which provides an available and low-cost approach for 3D device fabrication. More importantly, the theory of the damage layer proposed in this study can be naturally applied to relevant analyses on the eutectic reaction of other metals and single crystal materials.

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Advanced wafer bonding solutions for TSV integration with thin wafers

Cited by 11 publications

References 3 publications

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Fabrication of 3D Photonic Crystals toward Arbitrary Manipulation of Photons in Three Dimensions

The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

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