2017
DOI: 10.1088/1361-6439/aa99fe
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The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

Abstract: KOH etching and Au/Si eutectic bonding are cost-efficient technologies for 3D device fabrication. Aimed at investigating the process compatibility of KOH etching and Au/Si bonding, KOH etching tests have been carried out for Au/bulk Si and Au/amorphous Si (a-Si) bonding wafers in this paper. For the Au/bulk Si bonding wafer, a serious underetch phenomenon occurring on the damage layer in KOH etching definitely results in packaging failure. In the microstructure analysis, it is found that the formation of the d… Show more

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Cited by 3 publications
(4 citation statements)
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References 19 publications
(23 reference statements)
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“…As illustrated in [19], the adequate Au-Si eutectic reaction would result in the formation of the continuously distributed damage layer on the interface of Au-Si alloys and the bulk Si, which has been well-reasonably considered as the root cause of underetch phenomenon in KOH etching for the Au/bulk Si bonding structure. In order to protect the formed damage layer from KOH etching, it should be insulated between the Au-Si reaction interfaces and the exposed etching zones.…”
Section: Designmentioning
confidence: 99%
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“…As illustrated in [19], the adequate Au-Si eutectic reaction would result in the formation of the continuously distributed damage layer on the interface of Au-Si alloys and the bulk Si, which has been well-reasonably considered as the root cause of underetch phenomenon in KOH etching for the Au/bulk Si bonding structure. In order to protect the formed damage layer from KOH etching, it should be insulated between the Au-Si reaction interfaces and the exposed etching zones.…”
Section: Designmentioning
confidence: 99%
“…Still, due to the formed damage layer resulted from the Si-based eutectic reaction, we ever discussed the underetch phenomenon for the eutectic bonding (e.g. Au/ bulk Si bonding) in KOH etching [19]. Meanwhile, the Au/a-Si bonding structure adopted with a-Si as intermediate layer is illustrated to be compatible with KOH etching under certain conditions [19].…”
Section: Introductionmentioning
confidence: 99%
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“…Furthermore, the well-established fabrication process ensures consistent uniformity and a high yield [139][140][141][142][143]. The top-down approaches encompass various transfer methods, including silicon-on-insulator (SOI) [144][145][146][147][148][149], <111> wafer undercut etching [34,139,[150][151][152][153], metal-assisted chemical etching (MACE) [154][155][156][157], epitaxy-free methods [158][159][160][161], crack-based exfoliation [162][163][164][165][166], and bonding technology [128,167,168].…”
Section: Introductionmentioning
confidence: 99%