Advanced simulation technology for etching process design for CMOS device applications

Abstract

Plasma etching is a critical process for the realization of high performance in the next generation of CMOS devices. To predict and control fluctuations in the etching properties accurately during mass production, it is essential that etching process simulation technology considers fluctuations in the plasma chamber wall conditions, the effects of by-products on the critical dimensions, the Si recess dependence on the wafer open area ratio and local pattern structure, and the time-dependent plasma-induced damage distribution associated with the three-dimensional feature scale profile at the 100 nm level. This consideration can overcome the issues with conventional simulations performed under the assumed ideal conditions, which are not accurate enough for practical process design. In this article, these advanced process simulation technologies are reviewed, and, from the results of suitable process simulations, a new etching system that automatically controls the etching properties is proposed to enable stable CMOS device fabrication with high yields.

Plasma etching of high aspect ratio features in SiO2 using Ar/C4F8/O2 mixtures: A computational investigation

“…6 Results from a voxel-slab model, developed to investigate contact hole etching in SiO 2 , indicated that physical damage was reduced by maintaining a critical thickness of the overlaying polymer. 17,34 Bowing during the etching of HAR features was found to result from excessive fluxes of F and O radicals to the sidewalls according to the results of a line-of-sight profile simulator. 35 A model addressing pattern deformation and experimental measurements by atomic force microscopy indicated that the ratio of line width roughness to line edge roughness decreases with increasing etch depth, and the depth at which twisting occurs is shallower for a lower bias power.…”

Improvement of the plasma‐induced defect generation model in Si substrates and the optimization design framework

“…[1] Despite advancements in plasma processing, the degradation of material properties due to plasma exposure-plasma process-induced damage (PID)-has become a key issue. [2][3][4] In general, PID is classified on the basis of the mechanisms of its generation such as "physical damage," [5][6][7][8] "charging damage," [4,[9][10][11][12] and "radiation damage." [13][14][15][16][17] Physical damage is induced by high-energy ion bombardment on Si substrates or other material surfaces.…”

Investigation of feature orientation and consequences of ion tilting during plasma etching with a three-dimensional feature profile simulator

“…20 Computational simulations of profile evolution in 3d have provided keen insights into fundamental processes and etch phenomena. [21][22][23][24][25][26] For example, surface roughening is a major concern in controlling CD. Guo and Sawin investigated the onset of surface roughening using a 3d cellular Monte Carlo simulation and reported that the angle of ion incidence onto the surface was a key parameter for determining the perpendicular and parallel ripples.…”

“…25 Kuboi et al investigated the time-evolution of plasma-induced damage during SiN etching in hydrofluorocarbon plasmas using a 3d voxel-slab model. 25,26 They demonstrated that the major source of silicon damage in the source/drain region was high energy hydrogen during the over-etch step.…”

“…Although the 3d-model developed for this investigation and described in Sec. II does contain features incorporated into prior 3d models, [21][22][23][24][25][26] this model was developed with the intent of being as completely general as possible. Although the discussion here is limited to investigations of etching of silicon in Cl 2 containing plasmas, the model is in principle applicable to any etching systems whose processes can be described by a reaction mechanism.…”