Advanced microlithography process with chemical shrink technology

Kanda, Takashi; Tanaka, Hatsuyuki; Kinoshita, Yoshiaki; Watase, Natsuo; Eakin, Ronald J.; Ishibashi, Takehiko; Toyoshima, Toshiyuki; Yasuda, Naoki; Tanaka, Mikihiro

doi:10.1117/12.388374

Cited by 18 publications

(10 citation statements)

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“…This was done to take advantage of a chemical shrink process that reduces the contact patterns dimensions uniformly along the image perimeter. As a result, after the chemical shrink, the contact patterns edge placement errors are dominated by the biased cut exposure 6,7 . …”

Section: Contact Patternmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.

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Section: Contact Patternmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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“…The resolution enhanced lithography with chemical shrink (RELACS) is an invention by Mitsubishi [4]. The principles of the operation of RELACS are discussed extensively in [4]. The method is based on the interdiffusion between the photo active compound (PAC) remaining around the side walls of a developed photoresist pattern and the proprietarily developed RELACS material [4].…”

Section: All-optical 035-m T-shaped Gate Lithographymentioning

confidence: 99%

“…For the I-line lithography, there are two categories of RETs, the chemical shrink and the phase shift masks. The resolution enhanced lithography with chemical shrink (RELACS) is an invention by Mitsubishi [4]. The principles of the operation of RELACS are discussed extensively in [4].…”

Section: All-optical 035-m T-shaped Gate Lithographymentioning

confidence: 99%

“…The principles of the operation of RELACS are discussed extensively in [4]. The method is based on the interdiffusion between the photo active compound (PAC) remaining around the side walls of a developed photoresist pattern and the proprietarily developed RELACS material [4]. We used high resolution I-line photoresist for the stem definition because high resolution I-line resist retains a great deal of its PAC after post exposure bake and developing.…”

Section: All-optical 035-m T-shaped Gate Lithographymentioning

confidence: 99%

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Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

Tabatabaie-Alavi

Shaw

Duval

2003

IEEE Trans. Semicond. Manufact.

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T-shaped gate formation is a major processing step in the fabrication of high-performance field-effect transistor FET-based III-V devices. Traditional bilayer or trilayer E-beam lithography methods using PMMA/(PMMA&PMAA) copolymers are high-cost options which also lack the required critical dimension control for manufacturing. Lithography methods that use only a single layer of PMMA for the formation of T-shaped gate stem, and routine I-line resist lithography for the tee-top, i.e., hybrid T-shaped gates, have been developed and extensively used in manufacturing. This approach has also been extended to the fabrication of deep submicron T-shaped gates using all I-line optical lithography. Both chemical shrinks and chromeless phase-shift resolution enhancement techniques have been investigated.Index Terms-Field-effect transistor, GaAs, T-shaped gate.

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“…Because RELACS process is based on the cross-linking of RELACS film and the resultant chemical attachment to the sidewall of photoresist patterns 11 , the influence of the photoresist volume around contact holes are expected not so important to affect the shrink amount. On the contrary, thermal flow and SAFIER make the use of the fluent property of photoresist film when it is baked around T g so that the shrink amount is thought to be dependent on the remaining photoresist volume.…”

Section: Bulk Effectmentioning

confidence: 99%

Strategy for sub-80-nm contact hole patterning considering device fabrication

et al. 2004

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As the required contact holes dimension (CD) reaches to the physical limit of the conventional lithography, the image quality formed in a photoresist film is degraded seriously. To overcome this obstacle, several process-based techniques for ArF lithography have been suggested and some of them are reported to show excellent feasibilities 1-4 . In this article, three primary techniques for sub-80nm contact holes patterning are examined. They are ArF thermal flow, ArF SAFIER (Shrink Assist Film for Enhanced Resolution) and ArF RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink). These techniques are originated from different reaction mechanisms and result in distinguished shrink behaviors. Contact holes CDs of different patterns diverge one another depending on the adapted shrink process even though the initial CDs are identical. This is so called a bulk effect and is compensated by the optical proximity correction (OPC) procedure. The relationship of pattern CDs between mask and wafer is used to extract the correction factor. For the shrink process, it is divided to an optical factor and a process factor, that is, the shrink behavior is analyzed in terms of mask error factor (MEF) and process error factor (PEF). The PEF is calculated from the proportionality of post-shrink CD to initial CD of photoresist patterns. Using the PEF, it is possible to characterize each shrink process in the view of CD controllability. Consequently, we classify the shrink processes for the production of 65nm node devices considering the shrink properties and the cost of ownership.

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Advanced microlithography process with chemical shrink technology

Cited by 18 publications

References 0 publications

Lithographic imaging-driven pattern edge placement errors at 10nm node

Lithographic imaging-driven pattern edge placement errors at 10nm node

Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

Strategy for sub-80-nm contact hole patterning considering device fabrication

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