Advanced DC-SF Cell Technology for 3-D NAND Flash

Aritome, S.; Noh, Yoohyun; Yoo, Hyunseung; Choi, Eun Suk; Joo, Heesoo; Ahn, Youngsoo; Han, Byeongho; Chung, Sung‐Jae; Shim, Keonsoo; Lee, Keun-Woo; Kwak, Sanghyon; Shin, Sung‐Chul; Choi, Iksoo; Nam, Sanghyuk; Cho, Gyu-Seog; Sheen, Dongsun; Pyi, Seung-Ho; Choi, Jongmoo; Park, Sung-Kye; Kim, Jinwoong; Lee, Seokkiu; Hong, Sung-Joo; Park, Sungwook; Kikkawa, Takamaro

doi:10.1109/ted.2013.2247606

Cited by 24 publications

(17 citation statements)

References 7 publications

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“…All these cells feature an ONO stack. Retention data on a floating-gate based 3D NAND [290] show comparable results, with higher V T shift but larger voltage window. …”

Section: D Nand Reliabilitymentioning

confidence: 80%

“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”

Section: D Nand Reliabilitymentioning

confidence: 99%

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…All these cells feature an ONO stack. Retention data on a floating-gate based 3D NAND [290] show comparable results, with higher V T shift but larger voltage window. …”

Section: D Nand Reliabilitymentioning

confidence: 80%

Section: D Nand Reliabilitymentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…Recently, 3D vertical FG type NAND cell arrays have been proposed to overcome the retention and overall reliability issues of 3D CT NAND cell arrays [32][33][34][35][36]. In this section, an overview of the proposed 3D FG cells and their main reliability problems is reported.…”

Section: D-fg Nandmentioning

confidence: 99%

Reliability of 3D NAND Flash Memories

2016

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In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical mechanisms impacting the reliability of 2D CT NAND will be addressed. Then, a review of the main problems experimentally observed in different 3D CT cell concepts is reported. Finally, 3D FG memory concept is briefly introduced in order to understand the related reliability implications, and a comparison between 3D CT and 3D FG arrays is provided in terms of reliability and expected performances

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“…However, owing to charge-spreading issues in CT cell of 3D NAND flash, several manufacturers have opted using FG as the memory element for their 3D NAND. [2][3][4][5][6][7] Recently, a 3D FG-NAND based on conventional-floating gate (C-FG) structure was manufactured.…”

Section: Introductionmentioning

confidence: 99%

“…8,9) Although the triangular nanowire provides fast P=E operations, it is not fond to be employed as vertical channel in 3D NAND flash architecture, whereas the punch and plug process favour cylindrical channel instead. [3][4][5][6][7]10) In addition, it also suffers from poor retention due to the charge-trapped around the triangular corners. To compensate both the programming time and data retention of GAA-FG, in this work, the tunnel barrier engineering concept of variable oxide thickness (VARIOT) [11][12][13][14][15][16] as tunnel layer is utilized.…”

Section: Introductionmentioning

confidence: 99%

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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Advanced DC-SF Cell Technology for 3-D NAND Flash

Cited by 24 publications

References 7 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of 3D NAND Flash Memories

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

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