Advanced cell structures for dynamic RAMs

Lu, Nicky

doi:10.1109/101.17236

Cited by 34 publications

(6 citation statements)

References 32 publications

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“…Main memory reliability is a key design concern for any system because when and how memory errors occur a ects overall system reliability. In particular, designers of reliabilitycritical systems such as enterprise-class computing clusters (e.g., cloud, HPC) and systems operating in extreme or hostile environments (e.g., military, automotive, industrial, extraterrestrial) take additional measures (e.g., custom components [46,47,[302][303][304][305][306][307][308], redundant resources [60,309,310]) to ensure that memory errors do not compromise their systems. Section 2.1.1 shows the bene ts of incorporating mechanisms to improve memory reliability.…”

Section: Study 1: Improving Memory Reliabilitymentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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Section: Study 1: Improving Memory Reliabilitymentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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“…Shrinking the sizes of components has allowed ever greater numbers of them to be fabricated on each wafer, increasing efficiency and reducing cost. A recent review by Lu [1] of developments in dynamic random access memory (DRAM) chips, which use complementary metal oxide semiconductor (CMOS) devices, illustrates the rate of development in this field. Ning and Tang f2] have provided a similar review of advances in the area of bipolar devices.…”

Section: Introductionmentioning

confidence: 99%

On-chip wiring for VLSI: Status and directions

Small

Pearson

1990

IBM J. Res. & Dev.

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“…Driven by phenomenal commercial development, DRAM density quadruples every two to three years. This rapid development in DRAM technology has been attributed to evolution in device, process and circuit-design technologies [1,2]. Traditionally, the main thrust has been in improving the signal charge, speed, reliability, density and power consumption [3,4].…”

Section: Introductionmentioning

confidence: 99%

A proposed SEU tolerant dynamic random access memory (DRAM) cell

Agrawal

Massengill²,

Gulati³

1994

IEEE Trans. Nucl. Sci.

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A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a selfcompensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over conventional l-T DRAM cells.

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Advanced cell structures for dynamic RAMs

Cited by 34 publications

References 32 publications

A Case for Transparent Reliability in DRAM Systems

A Case for Transparent Reliability in DRAM Systems

On-chip wiring for VLSI: Status and directions

A proposed SEU tolerant dynamic random access memory (DRAM) cell

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