Advanced 300mm 0.13&amp;#x03BC;m BCD technology from 5V to 80V with highly reliable embedded Flash

Iwamoto, Kunihiko; Kori, M.; Terada, C.; Doguchi, T.; Mihara, M.; Kasa, Yasushi; Ukai, Kenji; Ujiie, Yoshihiro; Uehara, Hiroki; Hamanaka, C.; Tanaka, B.; Wada, K.; Shimizu, Satoshi; Shukuri, S.; Izumi, Naoki; Mifuji, Michihiko

doi:10.1109/ispsd.2014.6856061

Cited by 9 publications

(2 citation statements)

References 3 publications

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“…The benchmarking data against the latest published data is shown in Fig.5 for NMOS. The low RonA version NMOS achieves state of the art RonA/BVdss tradeoff [2,5,6,7,8]. Process robustness for HV MOSFETs has been studied, to cover (1) +/-10% dose split for each implant step of drift, (2) Vth implant split of PWELL and (3) STI CD/overhead/trench depth split.…”

Section: B Hv Mosfetmentioning

confidence: 99%

A 0.18μm SOI BCD technology for automotive application

Yang¹,

Sim²,

Toner³

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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This paper presents a new SOI BCD technology at the 0.18 m node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25m .mm 2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT, excellent matching well resistor, capacitors, top thick Copper Metallization option, embedded memory (OTP, CEEPROM, etc.) are also offered on this comprehensive technology platform.

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Section: B Hv Mosfetmentioning

confidence: 99%

A 0.18μm SOI BCD technology for automotive application

Yang¹,

Sim²,

Toner³

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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“…1) Recently, R ON • A has been reduced utilizing a submicron Bipolar-CMOS-DMOS (BCD) process and silicon on insulator (SOI) technology. [2][3][4][5][6][7][8] The LDMOSFET fabricated by the SOI-BCD process achieved an R ON • A of 0.545 mΩ•cm 2 at a breakdown voltage of 95 V. 7) This R ON • A almost reaches the one-dimension theoretical limit, which is determined by the type of material used (in the case of Si, this theoretical limit is known as the Si limit). 9,10) On the other hand, a novel structure that makes it possible to reduce the R ON • A compared with that of the RESURF structure was proposed in the late 1990s.…”

Section: Introductionmentioning

confidence: 99%

Trench-gate-integrated superjunction lateral double-diffused MOSFET with low specific on-resistance

Ōnishi

Hashimoto

2015

Jpn. J. Appl. Phys.

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In this paper, a new low-voltage planar gate superjunction (SJ) lateral double-diffused MOSFET (LDMOSFET) is presented. The proposed trench-gate-integrated SJ-LDMOSFET is composed of a conventional planar gate structure and a trench gate structure extending into a drift region through a channel region, which helps reduce both drift resistance and channel resistance. By device simulation, we confirmed that current crowding near the top surface was alleviated by the spread of electron current into the drift region through the accumulation layer of the trench gate. As a result, the specific on-resistance (RON · A) of the trench-gate-integrated SJ-LDMOSFET can be reduced by increasing SJ thickness (TSJ), and the trench-gate-integrated SJ-LDMOSFET with a TSJ of 4 µm achieved an RON · A of 0.47 mΩ·cm2 at a breakdown voltage of 97 V. This is about 14% lower than the one-dimensional Si limit.

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Embedded Flash and EEPROM for Smart IoT

2018

Memories for the Intelligent Internet of Things

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Advanced 300mm 0.13μm BCD technology from 5V to 80V with highly reliable embedded Flash

Cited by 9 publications

References 3 publications

A 0.18μm SOI BCD technology for automotive application

A 0.18μm SOI BCD technology for automotive application

Trench-gate-integrated superjunction lateral double-diffused MOSFET with low specific on-resistance

Embedded Flash and EEPROM for Smart IoT

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