Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture

Liu, J.C.; Yaung, Dun–Nian; Sze, Jhy-Jyi; Wang, C.C.; Hung, Gene.; Wang, C.J.; Hsu, T. H.; Lin, R.J.; Wang, T.J.; Wang, W.D.; Cheng, Hon-Chen; Lin, J.S.; Tsai, Scott; Tsai, S.T.; Chuang, Chia-Wei; Hsu, Wen-Wei; Chen, S.Y.; Huang, Kwo-Shu; Wu, Wei-Cheng; Takahashi, Shinji; Tu, Y. L.; Tsai, C.S.; Lee, R.L.; Mo, Wenxiong; Shiu, F. J.; Chao, Ying-Chen; Wuu, Shou-Gwo

doi:10.1109/vlsit.2014.6894429

Cited by 13 publications

(6 citation statements)

References 1 publication

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“…The processed CIS wafer was bonded with a logic wafer, followed by backside illumination process including thin down, anti-reflection coating, a color filter, and a micro-lens array process [ 10 ].…”

Section: A 45 Nm Stacked Cmos Image Sensormentioning

confidence: 99%

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

Takahashi

Huang

Sze

et al. 2017

Sensors

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A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.

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Section: A 45 Nm Stacked Cmos Image Sensormentioning

confidence: 99%

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

Takahashi

Huang

Sze

et al. 2017

Sensors

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“…Two measurement samples, "Control" and "Experiment", fabricated with different implant conditions are prepared based on tsmc-internal 1.1um Bayer patterned color CMOS image sensors using N45-Stacked-CIS BSI process 10) . The identical metal-grid 11) , color-filter and micro-lens structures with Bayer CFA configuration are adopted for both samples; therefore the difference of QE curves due to a change of electrical cross-talk is expected.…”

Section: Methodsmentioning

confidence: 99%

[Papers] Quantum Efficiency Simulation and Electrical Cross-talk Index Development with Monte-Carlo Simulation Based on Boltzmann Transport Equation

Yamashita¹,

Minamitani

Uchiyama³

et al. 2018

MTA

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180 IntroductionAs the pixel size of a color CMOS image sensor (CIS) shrinks downto sub-micron size, cross-talk 1) becomes one of the critical issues of image quality deterioration 2) .Among several types of cross-talks, electrical cross-talk can be suppressed by the introduction of deep trench isolation (DTI) technology 3) between photodiodes (PDs). In section 2, BTE is briefly explained, followed by the Abstract This paper explains a new method to model a photodiode for accurate quantum efficiency simulation. Individual photo-generated particles are modeled by Boltzmann transport equation, and simulated by Monte-Carlo method. Good accuracy is confirmed in terms of similarities of quantum efficiency curves, as well as color correction matrices and SNR10s. Three attributes -"initial energy of the electron", "recombination of electrons at the silicon surface" and "impurity scattering" -are tested to examine their effectiveness in the new model. The theoretical difference to the conventional method with drift-diffusion equation is discussed as well.Using the simulation result, the relationship among the cross-talk, potential barrier, and distance from the boundary has been studied to develop a guideline for cross-talk suppression. It is found that a product of the normal distance from the pixel boundary and the electric field perpendicular to the Z-axis needs to be more than 0.02V to suppress the probability of electron leakage to the adjacent pixel to less than 10%.

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“…In addition, the defects induced by etching, which can degrade and even suppress SPAD operation, have been reduced by more than 10 times with this optimization process. In addition, the direct 3D connection technology enables smaller pitch and consequently better 3D connection quality [10], and the impact of the 3D connections have been significantly minimized with further process improvement [11]. Fig.…”

Section: Back-illuminated 3d-stacked Spadmentioning

confidence: 99%

“…In addition, a DCR of 55.4 cps/µm 2 and a jitter of 107 ps full width at half maximum (FWHM) at 2.5 V excess bias voltage are achieved, the lowest ever reported in a backilluminated 3D-stacked CMOS technology. This performance was reached through optimized 3D-stacking, with a tight control of damage, improved doping profiles, and an especially designed optical stack [9]- [11]. This performance was achieved through careful analysis of the devices via extensive TCAD [5] and JSSC'15 [6], (b) IEDM'16 [7].…”

Section: Introductionmentioning

confidence: 99%

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Lee

Ximenes

Parameswaran

et al. 2018

IEEE J. Select. Topics Quantum Electron.

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We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P + /Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/µm 2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420-920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

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Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture

Cited by 13 publications

References 1 publication

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

[Papers] Quantum Efficiency Simulation and Electrical Cross-talk Index Development with Monte-Carlo Simulation Based on Boltzmann Transport Equation

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

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