ADOPT-a CAD tool for analog circuit design

Lai, J.C.; Kueng, J.S.; Chen, H.C.; Fernandez, F.J.

doi:10.1109/101.938

Cited by 9 publications

(2 citation statements)

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“…The MOS transistor sizing is a technique that determines the device sizes and/or parameters such as transistor size, resistance, and capacitance in the given circuit topology [5]. This concept is reported to be adapted in DELIGHT.SPICE [18], ECSTACY and ADOPT [19,20]. Transistor sizes are adjusted/modified in an iterative fashion, in order to satisfactorily meet the user specifications, using algorithms like Newton-Raphson, Steepest Descent, etc.…”

Section: Optimization Based Designmentioning

confidence: 99%

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Mendhurwar

Sundani

Aggarwal

et al. 2011

Analog Integr Circ Sig Process

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There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.

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Section: Optimization Based Designmentioning

confidence: 99%

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Mendhurwar

Sundani

Aggarwal

et al. 2011

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Historically, the very first attempt towards analog DA were numerical optimization based. Systems such as DELIGHT.SPICE [15], ECSTACY [16], ADOPT [17], and ASTRX/OBLX [18] consider the sizing of the individual transistors in a given circuit topology as an optimization problem. Typically, these systems employ optimization algorithms, which iteratively adjust the individual transistor sizes in order to meet the constraints and objectives specified by the user.…”

Section: Previous Workmentioning

confidence: 99%