A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Mendhurwar, Kaustubha; Sundani, Harsh; Aggarwal, Priyanka; Raut, R.; Devabhaktuni, Vijay

doi:10.1007/s10470-011-9648-z

Cited by 6 publications

(1 citation statement)

References 46 publications

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“…On the other hand, analog circuit design is governed by human intervention, such as topology selection and the use of a full custom layout. For this reason, optimizing the designs of analog circuits often follows well-known design circuit architectures and focuses more on optimizing each sub-module [2][3][4][5] and on finding joint optimum points during the sub-module integration step [6][7][8][9][10][11]. Therefore, AMS circuit designs rely heavily on the know-how and creativity of the designer and require considerable amounts of time to adjust the design parameters so as to ensure proper system target performance.…”

Section: Introductionmentioning

confidence: 99%

Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition

2022

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An analog and mixed-signal (AMS) circuit that draws on machine learning while using a regression model differs in terms of the design compared to more sophisticated circuit designs. Technology structures that are more advanced than conventional CMOS processes, specifically the fin field-effect transistor (FinFET) and silicon-on-insulator (SOI), have been proposed to provide the higher computation performance required to meet various design specifications. As a result, the latest research on AMS design optimization has enabled enormous resource savings in AMS design procedures but remains limited with regard to reflecting the intended operating conditions in the design parameters. Hereby, we propose what is termed a supervised learning artificial neural network (ANN) as a means by which to define an AMS regression model. This approach allows for rapid searches of complex design dimensions, including variations in performance metrics caused by process–voltage–temperature (PVT) changes. The method also reduces the considerable computation expense compared to that of simulation-program-with-integrated-circuit-emphasis (SPICE) simulations. Hence, the proposed AMS circuit design flow generates highly promising output to meet target requirements while showing an excellent ability to match the design target performance. To verify the potential and promise of our design flow, a successive approximation register analog-to-digital converter (SAR ADC) is designed with a 14 nm process design kit. In order to show the maximum single ADC performance (6-bit∼8-bit resolution and few GS/s conversion speed), we have set three different ADC performance targets. Under all SS/TT/FF corners, ±6.25% supply voltage variation, and temperature variation from −40 ∘C to 80 ∘C, the designed SAR ADC using our proposed AMS circuit optimization flow yields remarkable figure-of-merit energy efficiency (approximately 15 fJ/conversion step).

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