Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information

Koller, Jeff; Athas, W.C.

doi:10.1109/phycmp.1992.615554

Cited by 119 publications

(69 citation statements)

References 3 publications

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“…Energy dissipation in resistance R is [1] Since E DISS depends upon R, so by reducing the on Resistance of PMOS network the energy dissipation can be minimized. The on resistance of the MOSFET is given by the first order approximation is [9][10], Where μ is the mobility, C OX is the specific oxide capacitance, V GS is the gate source voltage w is the width, L is the length and V TH is the threshold voltage.…”

Section: Fig 6: Equivalent Circuit For Charge Recovery Process In Admentioning

confidence: 99%

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Yasoda¹

2013

IOSRJEN

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-The power consumption of the electronic devices can be reduced by adopting different design styles.Adiabatic logic style is said to be an attractive solution for such low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. In analysis, two logic families, ECRL(Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compared with conventional CMOS logic for inverter and 2:1 multiplexer circuits. The proposed technique has less power dissipation when compared to the conventional CMOS design style.

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Section: Fig 6: Equivalent Circuit For Charge Recovery Process In Admentioning

confidence: 99%

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Yasoda¹

2013

IOSRJEN

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“…Adiabatic circuits are capable of operating with substantially less energy dissipation compared to conventional CMOS circuits [1]. There are several principles shared by adiabatic circuits.…”

Section: Introductionmentioning

confidence: 99%

Investigation of stepwise charging circuits for power-clock generation in Adiabatic Logic

Raghav

Bartlett

Kale

2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits.

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“…Intelligent Systems and Applications, 2015, 08, 45-50 discharging of load capacitance adiabatically is known as adiabatic switching [1,2]. The adiabatic charging principle gives a way to charge load capacitor/parasitic capacitors via a resistor without dissipating of energy [20]. As shown in Fig.2.…”

Section: Introductionmentioning

confidence: 99%

“…The adiabatic logic circuits utilize AC supply voltage instead of the DC supply voltage. In above circuit, the charge transferred is and the average current will be (Q is transferred charge to the load) so, the computed dissipated energy is [20]. The energy dissipation (EDISS) is highly depended upon , so the energy dissipation can be reduced by minimizing the of PMOS network.…”

Section: Introductionmentioning

confidence: 99%

“…The energy dissipation (EDISS) is highly depended upon , so the energy dissipation can be reduced by minimizing the of PMOS network. The first order approximation of is given as: [13,20,24]. The result due to the "adiabatic principle" is a very slow change in systems which dissipate less energy than the fast ones; due to dissipation rates are proportional to the rate of change [20].…”

Section: Introductionmentioning

confidence: 99%

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Design of Low Power Sequential Circuit by using Adiabatic Techniques

Ojha¹,

Rana²

2015

IJISA

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Abstract-Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.

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Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information

Cited by 119 publications

References 3 publications

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Investigation of stepwise charging circuits for power-clock generation in Adiabatic Logic

Design of Low Power Sequential Circuit by using Adiabatic Techniques

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