Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Abstract

-The power consumption of the electronic devices can be reduced by adopting different design styles.Adiabatic logic style is said to be an attractive solution for such low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. In analysis, two logic families, ECRL(Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compared with conventional CMOS logic for inverter and 2:1 multiplexer circuits. The proposed technique has less power dissipation when compared to the conventional CMOS design style.