Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation

Yamae, Taiki; Takeuchi, Naoki; Yoshikawa, Nobuyuki

doi:10.1088/1361-6668/ac2e9f

Cited by 9 publications

(4 citation statements)

References 36 publications

(47 reference statements)

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“…Figure 6(b) shows the measured operating margins of Ix, which represent the noise margins of the encoder. The operating margin is reasonably wide up to 3 GHz but shrinks significantly at higher frequencies in a similar way to the previous experiment [23]. This may be due to process variation and indicates the necessity of more robust circuit design for even higher operating frequencies.…”

Section: Methodssupporting

confidence: 79%

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Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

et al. 2022

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Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a lowlatency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-toparallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

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Section: Methodssupporting

confidence: 79%

“…The latency of delay-line clocking can be set to much shorter values than that of four-phase clocking. We demonstrated basic AQFP logic gates using delay-line clocking with a latency as short as 10-20 ps per gate [22,23].…”

Section: Introductionmentioning

confidence: 99%

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

et al. 2022

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“…The operating margin will, however, shrink when the clock frequency increases from 1 GHz to 5 GHz. We attribute this to the performance of the high-speed voltage driver (SQUID stack) used to obtain the output waveforms in this experiment as well as those in [27]. We hope to improve this output interface and the experimental setup in the future.…”

Section: Resultsmentioning

confidence: 98%

Low clock skew superconductor adiabatic quantum-flux-parametron logic circuits based on grid-distributed blocks

He¹,

Ayala²,

Zeng³

et al. 2022

Supercond. Sci. Technol.

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Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several stages of TLs by using passive splitters, creating multiple leaves at the final stage. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising 4 blocks with data interconnections between each other and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.

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“…Another clocking scheme is delay-line clocking [10], where a single alternating excitation current is used and transmission lines are inserted between levels to delay the clock. Delay-line clocking does not only allow for even lower latency, but also enables the phase-skipping operation [11], [12], reducing the number of path-balancing buffers.…”

Section: A Gate-level Clocking Schemesmentioning

confidence: 99%

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Lee,

Ayala,

De Micheli

2023

IEEE Trans. Appl. Supercond.

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Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family whose energy efficiency approaches theoretical limits. Because AQFP logic gates depend on a polyphase excitation current to perform their computation, gate fanins must arrive at the appropriate excitation phase. Such a technology constraint has conventionally been treated by inserting buffers to balance shorter paths. However, path balancing buffers account for a large portion of the circuit area, limiting the scalability of AQFP circuits. In this paper, we examine the necessity of AQFP design constraints and propose a more relaxed set of constraints which still guarantees the correct operation of AQFP sequential circuits. In particular, we propose to consider phase alignment instead of path balancing. Experimental results show that adopting the relaxed constraints reduces 73% of buffers on average, and up to 90% in some particularly-imbalanced benchmarks.

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Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation

Cited by 9 publications

References 36 publications

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Low clock skew superconductor adiabatic quantum-flux-parametron logic circuits based on grid-distributed blocks

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

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