Adaptive quantization for low-density-parity-check decoders

Chung, Cha-Hao; Ueng, Yeong-Luh; Lu, Ming-Che; Lin, Mao‐Chao

doi:10.1109/isita.2010.5649830

Cited by 7 publications

(7 citation statements)

References 18 publications

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“…We found that κ = 1 2 provides a good tradeoff between performance and implementation complexity. In this case, our approach reduces to that proposed in [23]. …”

Section: A Adaptive Quantization (Aq) Algorithmmentioning

confidence: 99%

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Morero

Castrillon

Ramos³

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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This paper presents a non-concatenated forward error correction (FEC) code suitable for applications in 100Gb/s optical transport networks (OTN). A typical requirement in this application is a net coding gain (NCG) > 10dB at a bit error rate (BER) of 10 −15 with an overhead (OH) of ∼ 20%. As discussed in [1], non-concatenated codes are the ultimate frontier in terms of performance for OTN applications, because of their superior performance, lower latency, and lower overhead than concatenated codes. However, a major stumbling block for the use of these codes has been the existence of BER floors at levels significantly higher than the required 10 −15 (typically 10 −10 ). In this paper we present a new coding scheme based on a low density parity check (LDPC) code with an expected net coding gain of 11.30dB at 10 −15 , 20% OH, and a codeword length of 24576 bits. This represents a significant improvement over the previous state of the art [2], based on a concatenated code with a codeword length of 74844 bits and 20.5% OH. The code is designed to minimize the BER floor while simultaneously reducing the memory requirements and the interconnection complexity of the iterative decoder [3]. Experimental results obtained with an FPGA-based hardware emulator demonstrate an NCG of 10.70dB at a BER of 10 −13 and no error floors. These experimental results are extrapolated to 10 −15 using importance sampling techniques, resulting in the expected performance stated above. Moreover, we find that fixed-point implementation is the main cause of error floors below 10 −13 . Based on this finding, we introduce a new low complexity postprocessing technique to push BER floors down to 10 −15 .

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“…We found that κ = 1 2 provides a good tradeoff between performance and implementation complexity. In this case, our approach reduces to that proposed in [23]. …”

Section: A Adaptive Quantization (Aq) Algorithmmentioning

confidence: 99%

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

Morero

Castrillon

Ramos³

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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“…The latter works focus also on variable bitwidth representations of data to achieve higher power savings, the main subject of [6,7]. In [11], a tri-mode decod ing which combines the versatility of 3 decoding algorithms to achieve a good tradeoff between coding losses and power gains is proposed, which combines distinct update rules.…”

Section: Re Lation To Prior Workmentioning

confidence: 99%

“…In [11], a tri-mode decod ing which combines the versatility of 3 decoding algorithms to achieve a good tradeoff between coding losses and power gains is proposed, which combines distinct update rules. Tun ing of the data representation bitwidth was explored similarly to [6,7,10], with varying degrees of success. When us ing algorithms with very low bitwidth requirements, higher gains are possible when compared to the proposed Min-Sum- XOR -AND -based approach which is more sensItIve to low bitwidths.…”

Section: Re Lation To Prior Workmentioning

confidence: 99%

“…Algorithms such as the MSA [2], SCMSA [3,4] and improved differential binary (IDB) [5], to name a few, were developed with this principle in mind. Furthermore, quantization strategies were also developed, static and dynamic [6,7], which minimize the required data bitwidth for the decoder design to have high coding gains. On the other hand, gear-shift techniques have been developed [6,7,8,9,10,11], which combine the versatility of adaptive quantization schemes with different decoding algorithms, or node update rules, in order to reach more flexible tradeoffs in both BER performance, energy efficiency of the decoder, decoding latency and throughput.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, quantization strategies were also developed, static and dynamic [6,7], which minimize the required data bitwidth for the decoder design to have high coding gains. On the other hand, gear-shift techniques have been developed [6,7,8,9,10,11], which combine the versatility of adaptive quantization schemes with different decoding algorithms, or node update rules, in order to reach more flexible tradeoffs in both BER performance, energy efficiency of the decoder, decoding latency and throughput. Existing gear-shift decoders work on the principle that a powerful decoding algorithm is not needed in all decoding iterations, but is required in order to improve on the least powerful algorithm work carried out in the previous itera tions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Accelerating and deceleratingmin-sum-based gear-shift LDPC decoders

Andrade

Falcão

Silva

2015

2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Low-Density Parity-Check (LDPC) decoders typically imple ment a single decoding algorithm or update rule, which nar rows down the design space of the decoder and maintains its overall simplicity. However, gear-shift techniques combine multiple decoding algorithms, update rules and quantization of the log-likelihood ratios (LLRs), allowing wider design space explorations as more parameters can be fine-tuned to a particular need. Gear-shift LDPC decoders have been shown to improve both the decoding throughput and the energy effi ciency per bit decoded, while achieving similar capacity com pared to traditional approaches that only use one algorithm. In this paper, we incorporate gear-shift techniques based on the Min-Sum algorithm (MSA) and Self-Corrected Min-Sum al gorithm (SCMSA) using variable quantization steps. The pro posed design allows bit error rate (BER) performances close to the more powerful SCMSA running only a selected number of iterations using the most powerful update rule.

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