Accelerating and deceleratingmin-sum-based gear-shift LDPC decoders

Abstract

Low-Density Parity-Check (LDPC) decoders typically imple ment a single decoding algorithm or update rule, which nar rows down the design space of the decoder and maintains its overall simplicity. However, gear-shift techniques combine multiple decoding algorithms, update rules and quantization of the log-likelihood ratios (LLRs), allowing wider design space explorations as more parameters can be fine-tuned to a particular need. Gear-shift LDPC decoders have been shown to improve both the decoding throughput and the energy effi ciency per bit decoded, while achieving similar capacity com pared to traditional approaches that only use one algorithm. In this paper, we incorporate gear-shift techniques based on the Min-Sum algorithm (MSA) and Self-Corrected Min-Sum al gorithm (SCMSA) using variable quantization steps. The pro posed design allows bit error rate (BER) performances close to the more powerful SCMSA running only a selected number of iterations using the most powerful update rule.