Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Wang, Zhe; Jiménez, Daniel; Xu, Cong; Sun, Guangyu; Xie, Yuan

doi:10.1109/hpca.2014.6835933

Cited by 103 publications

(84 citation statements)

References 24 publications

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“…Under the same area constraint across a collection of 30 workloads, the study found that such an aggressive hybrid cache design yields a 10% to 16% performance improvement over the baseline design with a level-3, SRAM-only c 2015 Information Processing Society of Japan cache design, and achieves up to a 72% power reduction. Wang et al [56] proposed an adaptive block placement and migration policy used in an SRAM/STT-MRAM hybrid last-level cache. The proposed mechanism improves both performance and power by placing a block into either SRAM or STT-MRAM by adapting to the access pattern of writes that are categorized as prefetching, demand, and core access.…”

Section: Processor Cache Design With Nvmsmentioning

confidence: 99%

Memory and Storage System Design with Nonvolatile Memory Technologies

Zhao

Chi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Abstract:The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.

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Section: Processor Cache Design With Nvmsmentioning

confidence: 99%

Memory and Storage System Design with Nonvolatile Memory Technologies

Zhao

Chi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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“…Hence, a large body of work has been focused on replacing SRAM cells with STT-RAM cells in on-chip cache memories. Due to their low leakage power consumption, large scale last-level caches (L2 or L3 caches) have been an attractive candidate for STT-RAM deployment [2,3,5,8]. In addition, there have been several studies that utilize STT-RAM cells for L1 cache memories [1,4,6,7].…”

Section: Related Workmentioning

confidence: 99%

“…However, a major impediment to employ STT-RAM cells in on-chip caches has been their inferior write performance and energy-efficiency compared to conventional SRAM cells. Thus, the main focus of the previous studies is to mitigate an adverse impact of write operations in STT-RAM cells deployed for on-chip caches [1,2,3,4,5,6,7,8].…”

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confidence: 99%

A novel technique for technology-scalable STT-RAM based L1 instruction cache

Kong

2016

IEICE Electron. Express

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STT-RAM is an emerging memory cell to construct on-chip memories or caches. However, in advanced process technology, it is known that STT-RAM cells are vulnerable to read disturbance. To employ STT-RAM cells in on-chip caches for better energy-and cost-efficiency, appropriate techniques to prevent or avoid read disturbance are essential. In this paper, we propose a novel architectural technique to enable an energy-and performance-efficient STT-RAM based L1 instruction caches for future process technologies. Our selective way access with a write line buffer adopts a sequential cache access between the MRU way and non-MRU way, reducing energy overhead from the data restoring after the read operation. In addition, the write line buffer hides a latency of currently pending or on-going write operations in L1 instruction caches, minimizing stalls in processor pipelines. Our proposed techniques improve performance per Watt of the STT-RAM based L1 instruction cache by 1.6X and 2.6X compared to the conventional SRAM-based cache (denoted as SRAM in this paper) and STT-RAM based cache with the naive data restoring (denoted as STTRAM_dr in this paper).

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“…However, many of those proposals focus on energy reduction in L2 or lastlevel caches which exploit lower leakage power consumption and smaller cell area of STTRAM cells compared to SRAM cells [1][2][3][4][5][6][7]. Several proposals have been introduced for STTRAM-based L1 caches.…”

Section: Related Workmentioning

confidence: 99%

“…They have significantly lower leakage energy consumption and smaller cell size with comparable (or less) read access energy and latency compared to the conventional 6T SRAM cells. Due to their better leakage energy efficiency, there have been many proposals to use STTRAM cells for on-chip caches [1][2][3][4][5][6][7]. However, the main disadvantages of STTRAM cells are high write energy and latency.…”

Section: Introductionmentioning

confidence: 99%

A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

Kong

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%. Index Terms-Spin torque transfer random access memory, filter cache, energy efficiency, performance, L1 data cache

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Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Cited by 103 publications

References 24 publications

Memory and Storage System Design with Nonvolatile Memory Technologies

Memory and Storage System Design with Nonvolatile Memory Technologies

A novel technique for technology-scalable STT-RAM based L1 instruction cache

A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

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