A novel technique for technology-scalable STT-RAM based L1 instruction cache

Kong, Joonho

doi:10.1587/elex.13.20160220

Cited by 6 publications

(4 citation statements)

References 14 publications

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“…Also, they adopted a write buffer scheme to hide long write latency for MRAM, which is widely used in many other previous work on MRAM-based on-chip caches [ [41]. In addition to MRAM-based large caches, several researchers proposed MRAM-based register files [17] and L1 caches [20] [36], which also avoid long MRAM write latency based on small write buffers.…”

Section: B Non-volatile Memory (Nvm)mentioning

confidence: 99%

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Gong

2021

IEEE Access

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Monolithic 3D (M3D) integration has been emerged as a promising technology for finegrained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as caches, register files, translation look-aside buffers (TLBs), etc. However, since the M3D integration requires low-temperature process for stacked layers, it causes lower performance for stacked transistors compared to the conventional 2D process. In contrast, non-volatile memory (NVM) such as magnetic RAM (MRAM) is originally fabricated at a low temperature, which enables the M3D integration without performance degradation. In this paper, we propose an energy-efficient unified L2 TLB-cache architecture exploiting M3D-based SRAM/MRAM hybrid memory. Since the M3D-based SRAM/MRAM hybrid memory consumes much smaller energy than the conventional 2D SRAM-only memory and 2D SRAM/MRAM hybrid memory, while providing comparable performance, our proposed architecture improves energy efficiency significantly. Especially, as our proposed architecture changes the memory partitioning of the unified L2 TLB-cache depending on the L2 cache miss rate, it maximizes the energy efficiency for parallel workloads suffering extremely high L2 cache miss rate. According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB+L2 cache by up to 97.7% (53.6% on average), compared to the baseline with the 2D SRAM-only memory, with negligible impact on performance. Furthermore, our proposed technique reduces the memory access energy consumption by up to 32.8% (10.9% on average), by reducing memory accesses due to TLB misses.

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Section: B Non-volatile Memory (Nvm)mentioning

confidence: 99%

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Gong

2021

IEEE Access

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“…5) Other researchers have proposed architectural management techniques, such as phased access of MRU and non-MRU ways [23], avoiding restore operations by using LCLL reads [11], data compression [24], data-duplication [24], by exploiting cache/register-file access properties [10], [25] and by using an SRAM buffer to absorb reads for minimizing reads from STT-RAM [25]. By comparison, some techniques postpone restores by scheduling them at idle times.…”

Section: E Strategies For Addressing Rdementioning

confidence: 99%

Mitigating Read Disturbance Errors in STT-RAM Caches by Using Data Compression

Mittal

2019

Nanoelectronics

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Due to its high density and close-to-SRAM read latency, spin transfer torque RAM (STT-RAM) is considered one of the most-promising emerging memory technologies for designing large last level caches (LLCs). However, in deep sub-micron region, STT-RAM shows read-disturbance error (RDE) whereby a read operation may modify the stored data value and this presents a severe threat to performance and reliability of STT-RAM caches. In this paper, we present a technique, named SHIELD, to mitigate RDE in STT-RAM LLCs. SHIELD uses data compression to reduce number of read operations from STT-RAM blocks to avoid RDE and also to reduce the number of bits written to cache during both write and restore operations. Experimental results have shown that SHIELD provides significant improvement in performance and energy efficiency. SHIELD consumes smaller energy than two previous RDE-mitigation techniques, namely high-current restore required read (HCRR, also called restore-after-read) and low-current long latency read (LCLL) and even an ideal RDE-free STT-RAM cache. Index TermsNon-volatile memory (NVM), cache memory, STT-RAM, read disturbance error, data compression, reliability. I. INTRODUCTIONRecent trends of increasing core-counts and LLC capacity have motivated researchers to explore low-leakage alternatives of SRAM for designing large LLCs. Due to their high density and near-zero leakage power consumption, non-volatile memories such as STT-RAM and ReRAM (resistive RAM) have received significant attention in recent years[1], [2]. Of these, STT-RAM is considered especially suitable for designing LLCs due to its close-to-SRAM read latency and high write endurance [3].Since the write latency/energy of STT-RAM are higher than those of SRAM, previous work has mainly focused on addressing this overhead to enable use of STT-RAM for designing on-chip caches [4]. However, a more severe issue of 'read disturbance error' (RDE) in STT-RAM caches has not been adequately addressed. Specifically, with feature size scaling, the write current reduces, however, read current does not reduce as much [5]. In fact, for sub-32nm feature size, the magnitude of read current becomes so close to the write current that a read operation is likely to modify the stored data and this is referred to as RDE (refer Section II for more details). Since reads happen on critical access path, RDE is likely to severely affect performance and reliability. In fact, it is expected that with ongoing process scaling, readability and not writability will become the most crucial bottleneck for STT-RAM [6], [7], [8], [9].Contributions: In this paper, we present a technique, named 'SHIELD', which shields STT-RAM caches against both RDE and high write latency/energy overhead. SHIELD works by using data compression to reduce the number of S. Mittal is with IIT Hyderabad, India.

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“…Plus, hybrid cache architecture (HCA) was introduced [18] to reduce the write-intensity of NVM by containing SRAM cells as well as NVM cells in the same structure. It can be applied from L1 cache level [19] [20] to last-level cache [21] or main memory [22][23] [24]. In addition, FPGA or IoT devices are also objectives of HCA studies [25][26] [27].…”

Section: Introductionmentioning

confidence: 99%

A method of defense against cache timing attack in non-volatile memory

Choi

2023

IEICE Electron. Express

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Attackers of modern computer architecture found that cache access latency difference between cache hit and cache miss is a point where secure data are overlooked. To prevent such data leakage, cache partitioning technique is utilized for defenders via cache hit isolation. Although this approach is effective in increasing resistance against cache timing attack, it is not suitable for emerging memory system, which is based on non-volatile memories, because it overlooks the weaknesses of the write operations. This paper proposes a secure-aware partitioning guide architecture to improve performance and write endurance by removing the necessity of cache flushing. During changing cache partitioning status, the write counts are considered for the new status and no cache lines are evicted in the proposal. As a result, the lifetime is extended by 1.77 times and the penalty of cache flushing is saved by 7.8%.

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A novel technique for technology-scalable STT-RAM based L1 instruction cache

Cited by 6 publications

References 14 publications

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Mitigating Read Disturbance Errors in STT-RAM Caches by Using Data Compression

A method of defense against cache timing attack in non-volatile memory

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