2017 IEEE Aerospace Conference 2017
DOI: 10.1109/aero.2017.7943580
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Adaptive compression schemes for housekeeping data

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Cited by 8 publications
(6 citation statements)
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“…All other bits are cut to save downlink budget. The complete compression scheme is described in [9]. From a reliability point of view, although the OR1200 processors on the FPGAs and especially their memories and registers are hardened by duplication or triplication of some of the underlying flip-flops, there is no redundancy at the unit or system level.…”
Section: Fig 1 Data Flowmentioning
confidence: 99%
“…All other bits are cut to save downlink budget. The complete compression scheme is described in [9]. From a reliability point of view, although the OR1200 processors on the FPGAs and especially their memories and registers are hardened by duplication or triplication of some of the underlying flip-flops, there is no redundancy at the unit or system level.…”
Section: Fig 1 Data Flowmentioning
confidence: 99%
“…(a) the gain α k was set to a constant for all k, and it was adjusted to obtain the same effect of the prefactor parameter defined in [24] for the tests with N = 256, (b) the compression rate was computed using the same criteria detailed by Mess et al [24], that is, with no entropy code and a header to inform the position of non-zero coefficients, see also [25].…”
Section: Resultsmentioning
confidence: 99%
“…In summary, the figure 4 shows the performance of the method introduced in [24,25] to the first axis of Mission B.…”
Section: Resultsmentioning
confidence: 99%
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