Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance

Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices

“…Advanced MOSFETs rely heavily on the use of Strained Silicon (SS) process to impart performance boost to existing devices (nMOS and pMOS) [3]. SS works by imparting mechanical stress to the channel of a device which significantly boosts the mobility of carriers.…”

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

“…In the 90 nm test-chip, it was shown that line width variation caused by the poly-Si pitch cause these structures to print differently, giving rise to different transistor performance [18]. D1 has a longer source/drain (S/D) diffusion area than P3, which has been observed to cause different strain in a transistor [16]. M1 has metal-2 coverage over its gate which has been shown to cause different annealing temperatures [19] during the process of rapid thermal annealing.…”

“…Traditional methods use SiO in the STI trenches, which create compressive strain on the channel substrate that varies with distance from the edge of the STI/diffusion interface to the channel region [16]. In this 45 nm process, the use of sub-atmospheric chemical vapor deposition oxide Fig.…”

Metrology (including Materials Characterization) for Nanoelectronics

“…The first high volume ICs with channel engineering appeared at the 90 nm node [14][15][16][17][18]. a variety of processes were used to improve electron and hole mobility.…”