Accelerating run-time reconfiguration on FCCMs

Heron, J.; Woods, Roger

doi:10.1109/fpga.1999.803688

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…Three broad classes of partitioning techniques are identified from literature survey -1) partitioning of a large circuit to fit into a programmable device, 2) partitioning circuit into static and dynamic part and 3) partitioning configuration bitstreams. Initial work in [11], [12] have focussed the efforts to reduce reconfiguration time for specific applications by partitioning the design into static and dynamic sections by design level inspection. A pipelined neural network implemented in [11] demonstrates the reduction in reconfiguration time by isolating static circuitry common to the different functions in the pipeline.…”

Section: Related Workmentioning

confidence: 99%

“…The dynamic reconfigurable circuit is the circuitry that is left after removing the static part. In a similar vein, the work in [12] utilizes architecturally similar implementations of multiply, divide and square root operations to extract a common static circuit for the three operations for reducing reconfiguration time. These techniques do not apply for arbitrary multi-level combinational circuits and no clear methodology is discussed for automation.…”

Section: Related Workmentioning

confidence: 99%

“…These techniques do not apply for arbitrary multi-level combinational circuits and no clear methodology is discussed for automation. Higher level abstraction such as design source code, where there is clear demarcation of functionalities, is required to take advantage of techniques in [11], [12].…”

Section: Related Workmentioning

confidence: 99%

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Partial reconfiguration logic synthesis by temporal slicing

Ponpandi

Tyagi

2011

2011 International Conference on Field-Programmable Technology

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Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set to optimize the hardware circuit for reduction in area. We show that reduced area dynamic reconfigurable slices can be generated for combinational circuits with minimal effect on the critical path. The results reported for MCNC logic synthesis benchmark circuits show an average 40% reduction in area for logic slices.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Partial reconfiguration logic synthesis by temporal slicing

Ponpandi

Tyagi

2011

2011 International Conference on Field-Programmable Technology

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“…They perform partial reconfiguration to reduce the reconfiguration overhead. Turner and Woods [6] have suggested a method to form reconfiguration sets by maximizing the static hardware between reconfigurations and achieve speed-up using partial reconfiguration. Schwabe et al [7] take advantage of some of the features of the Xilinx XC6200 family of FPGAs to reduce the reconfiguration time overhead by compression of the configuration bit streams.…”

Section: Related Workmentioning

confidence: 99%

An integrated temporal partioning and partial reconfiguration technique for design latency improvement

Ganesan

Vemuri

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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Partially reconfigurable processors provide the unique ability by which a part of the device can be reconfigured, while the remaining part is still operational. In this paper, we present a novel partitioning methodology that temporally partitions a design for such a partially reconfigurable processor and improves design latency by minimizing reconfiguration overhead. This is achieved by overlapping execution of one temporal partition with the reconfiguration of another, using the processors partial reconfiguration capability. We have incorporated block-processing in the partitioning framework for reducing reconfiguration overhead of partitioned designs. A highlight of our partitioner is it's ability to handle loops and conditional constructs in the input specification. The proposed methodology was tested on several examples on the Xilinx 6200 FPGA. The results show significant reduction in the design latency, leading to a considerable speed-up due to partial reconfiguration.

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An integrated temporal partitioning and partial reconfiguration technique for design latency improvement

Ganesan¹,

Vemuri²

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)

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Accelerating run-time reconfiguration on FCCMs

Cited by 4 publications

References 4 publications

Partial reconfiguration logic synthesis by temporal slicing

Partial reconfiguration logic synthesis by temporal slicing

An integrated temporal partioning and partial reconfiguration technique for design latency improvement

An integrated temporal partitioning and partial reconfiguration technique for design latency improvement

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