An integrated temporal partitioning and partial reconfiguration technique for design latency improvement

Ganesan, S.; Vemuri, Ranga

doi:10.1109/date.2000.840290

Cited by 10 publications

(11 citation statements)

References 4 publications

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“…High level specification of the design to be reconfigured is partitioned into pipelined modules with the goal of amortizing the cost of reconfiguration in [13]. Successive module pairs of the pipeline are executed and reconfigured simultaneously to mask the reconfiguration cost of the second stage.…”

Section: Related Workmentioning

confidence: 99%

“…Partitioning of a large design into pipelined functions such that each pipeline stage is reconfigured one at a time is the central idea of the work in [13], [3], [14], [15], [16]. High level specification of the design to be reconfigured is partitioned into pipelined modules with the goal of amortizing the cost of reconfiguration in [13].…”

Section: Related Workmentioning

confidence: 99%

“…Similarly, sequential circuits are k-partitioned in [15], [16]. Drawback of the approaches in [13], [3], [14] is that the negative impact of k-partitioning on important attributes, such as critical path of the original design, has not been addressed. Such partitioning solutions made sense for small FPGA chips.…”

Section: Related Workmentioning

confidence: 99%

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Partial reconfiguration logic synthesis by temporal slicing

Ponpandi

Tyagi

2011

2011 International Conference on Field-Programmable Technology

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Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set to optimize the hardware circuit for reduction in area. We show that reduced area dynamic reconfigurable slices can be generated for combinational circuits with minimal effect on the critical path. The results reported for MCNC logic synthesis benchmark circuits show an average 40% reduction in area for logic slices.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Partial reconfiguration logic synthesis by temporal slicing

Ponpandi

Tyagi

2011

2011 International Conference on Field-Programmable Technology

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“…Despite an increasing number of modern FPGAs providing partial run-time reconfiguration-two core requirements for dynamic reconfiguration-methods that allow to exploit these additional flexibilities are rarely found. Nevertheless, some work has been done that proofs the benefit of fine grain granularity and high adaptability of FPGAs, e. g. in [3,4,5,6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Algorithmic Skeletons for the Programming of Reconfigurable Systems

Dittmann

2007

Software Technologies for Embedded and Ubiquitous Systems

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Abstract. Reconfigurable hardware such as FPGAs combines performance and flexibility, two inherent requirements of many modern electronic devices. Moreover, using reconfigurable devices, time to market can be reduced while simultaneously cutting the costs. However, the design of systems that beneficially explore the reconfiguration capabilities of modern FPGAs is cumbersome and little automated. In this work, a new approach is described that starts from a very high level of abstraction, so-called algorithmic skeletons, and exploits the additional information of this level of abstraction to beneficially execute on reconfigurable devices. Particularly, the approach focuses on dynamic run-time reconfiguration on partially reconfigurable FPGAs. As a first introduction to this approach, we consider stream parallelism paradigms including their composition.

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“…Those schemes only consider another partition after the current one has filled the available resources and are insensible to the optimization that must be applied to reduce the overall execution by overlapping the fetching, configuring and computing steps. One of the first attempts to reduce the configuration overhead in the context of temporal partitioning has been presented in [14]. They attempt to overlap configuring with computing of adjoining partitions.…”

Section: Related Workmentioning

confidence: 99%