2021 IEEE Hot Chips 33 Symposium (HCS) 2021
DOI: 10.1109/hcs52781.2021.9566904
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Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip

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Cited by 17 publications
(6 citation statements)
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“…For example, this is how the communication subsystem is organized in Intel Xeon E5 class processors (it even received the name Intel The idea of organizing a communication subsystem in a NoC in the form of a finegrained mesh-like structure turned out to be very convenient and has been the main one in the NoC design for a long time. For example, this is how the communication subsystem is organized in Intel Xeon E5 class processors (it even received the name Intel Mesh Interconnect) [15,16] or the ET-SoC-1 chip [17] from Esperanto Technologies consisting of 1089 + 4 64-bit RISC-V processor units. Also, with the imperfection of CAD tools for the synthesis of integrated circuits, it is convenient to use simplification when designing and representing individual macroblocks of the network in the form of rectangles compactly located on the die area.…”
Section: Topological Approachmentioning
confidence: 99%
“…For example, this is how the communication subsystem is organized in Intel Xeon E5 class processors (it even received the name Intel The idea of organizing a communication subsystem in a NoC in the form of a finegrained mesh-like structure turned out to be very convenient and has been the main one in the NoC design for a long time. For example, this is how the communication subsystem is organized in Intel Xeon E5 class processors (it even received the name Intel Mesh Interconnect) [15,16] or the ET-SoC-1 chip [17] from Esperanto Technologies consisting of 1089 + 4 64-bit RISC-V processor units. Also, with the imperfection of CAD tools for the synthesis of integrated circuits, it is convenient to use simplification when designing and representing individual macroblocks of the network in the form of rectangles compactly located on the die area.…”
Section: Topological Approachmentioning
confidence: 99%
“…State-of-the-art Supercomputers on chip (SoC) examples encourage this approach [7,12,38,53]. Future SoC will have all the above-mentioned components in a package, each one as a separate chipset, connected with a high bandwidth on-package interface in a 3D manner.…”
Section: Possible Architecture Of a Supercomputer On A Chipmentioning
confidence: 99%
“…11 MIT, Boston, MA, USA. 12 Technion, Haifa, Israel. 13 Harvard University Medical School, Boston, USA.…”
Section: Author Contributionsmentioning
confidence: 99%
“…The development of multiprocessor systems-on-chip (MPSoCs) has become a ubiquitous trend and has led to the fact that modern chips can accommodate tens, hundreds or even thousands of processor cores. So, the latest versions of the WSE2 chip from Cerebras can contain up to 850,000 computing cores [1,2], and the project from Esperanto technologies promises 1088 energy-efficient ET-Minion 64-bit RISC-V each with a vector/tensor unit in ET-SoC-1 chip [3]. The operation of such large MPSoCs is not possible without a high-performance communication subsystem, the tasks of which are currently performed by the network-on-chip (NoC).…”
Section: Introductionmentioning
confidence: 99%
“…It should be noted that circulant graphs of dimensions 2 and 3 are used as topologies of multiprocessor systems [15,20,21], and also as promising topologies of NoCs [5,8]. Modern chips already can have more than 1000 cores [1][2][3]. For the most part, they are still connected by mesh topology, but at the same time (due to the large number of nodes), the distance between nodes is too large, which is to be corrected by global ring connections (for example, over a wireless channel [23,24]).…”
Section: Introductionmentioning
confidence: 99%