Accelerating HEVC using heterogeneous platforms

Cebrián-Márquez, Gabriel; Hernández-Losada, J.L.; Martínez, José Luis; Cuenca, Pedro; Tang, Minhao; Wen, Jiangtao

doi:10.1007/s11227-014-1313-8

Cited by 14 publications

(4 citation statements)

References 12 publications

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“…Usually, most of the GPU video coding implementations deal with motion estimation schemes with relaxed dependencies, as proposed in [16,17] for HEVC and in [18] for H.264/ MPEG-4 AVC. However, efficient GPU approaches for HEVC decoding are yet to be derived, especially for intra decoding.…”

Section: Related Workmentioning

confidence: 99%

GPU-assisted HEVC intra decoder

Souza

Ilić

Roma

et al. 2015

J Real-Time Image Proc

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The added encoding efficiency and visual quality offered by the High Efficiency Video Coding (HEVC) standard is attained at the cost of a significant computational complexity of both the encoder and the decoder. In particular, the considerable amount of intra prediction modes that are now considered by this standard, together with the increased complexity of the adopted block coding tree structures using a larger diversity of transforms imposes demanding computational efforts that can hardly be satisfied by current general-purpose processors to attain hard real-time requirements. Furthermore, the strict data dependencies that are imposed make parallelization a difficult and hardly efficient option with conventional approaches. To circumvent this adversity, this paper exploits Graphics Processing Units (GPUs) to accelerate the intra decoding procedure in HEVC, encompassing the most demanding modules of the decoder (i.e., de-quantization, inverse transform, intra prediction, deblocking filter, and sample adaptive offset). The presented approaches comprehensively exploit both coarse and fine-grained parallelization opportunities in an integrated perspective by redesigning the execution pattern of the involved modules, while simultaneously coping with their inherent computational complexity and strict data dependencies. As a result, the proposed parallelization, which is fully compliant with the HEVC standard, has shown to be a remarkable viable approach, being capable of satisfying hard real-time requirements by processing each Ultra HD 4 K intra frame in less than 25 ms (about 40 fps).

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Section: Related Workmentioning

confidence: 99%

GPU-assisted HEVC intra decoder

Souza

Ilić

Roma

et al. 2015

J Real-Time Image Proc

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“…There have been some works to reduce the computational complexity of ME using GPU based on the new generation of video codec. Some works focus on the improvements of algorithm architecture [8], [9]. In [8], the IME is divided into two steps and applied on a GPU.…”

Section: Introductionmentioning

confidence: 99%

“…In [8], the IME is divided into two steps and applied on a GPU. For better combining the previous parallelization techniques on CPU, [9] proposed two joint algorithms which are based on WPP and on a traditional GOP-based division pattern. On the other hand, the effective parallel implementation of crucial parts in ME is very important [10], [11].…”

Section: Introductionmentioning

confidence: 99%

A Novel Parallel Motion Estimation Design and Implementation on GPU

Zhang

Zhao

et al. 2019

IEEE Access

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The development of high-resolution video mounts a serious challenge to the previous video coding standard. The appearance of the new generation standards greatly relieves the dilemma but increases the coding complexity dramatically. Motion estimation is considered as the module with a relatively high computational complexity. In this paper, a parallel motion estimation implementation is proposed, which includes pre-motion estimation, integer motion estimation, and fractional motion estimation. They are highly accelerated on GPU based on AVS2, which is one of the new generation standards. A rapid mapping table algorithm is introduced to improve the efficiency of data access. In addition, a quasi-integral-graph algorithm is designed to calculate SAD or SATD efficiently for blocks of different sizes. The two novel techniques can effectively improve the utilization and efficiency of threads and exploit the characteristics of GPU. The experimental results show that the proposed parallel method can effectively accelerate the motion estimation.

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“…Although HEVC decoder implementations are already proposed for multi-core Central Processing Units (CPUs) [4] and Field-Programmable Gate Arrays (FPGAs) [5], the existing Graphics Processing Unit (GPU) approaches are limited to only a certain set of HEVC modules, namely motion estimation [6], deblocking filtering [7] and inverse transform [8].…”

Section: Introductionmentioning

confidence: 99%

Towards GPU HEVC intra decoding: Seizing fine-grain parallelism

Souza

Ilić

Roma

et al. 2015

2015 IEEE International Conference on Multimedia and Expo (ICME)

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To satisfy the growing demands on real-time video decoders for high frame resolutions, novel GPU parallel algorithms are proposed herein for fully compliant HEVC de-quantization, inverse transform and intra prediction. The proposed algorithms are designed to fully exploit and leverage the fine grain parallelism within these computationally demanding and highly data dependent modules. Moreover, the proposed approaches allow the efficient utilization of the GPU computational resources, while carefully managing the data accesses in the complex GPU memory hierarchy. The experimental results show that the real-time processing is achieved for all tested sequences and the most demanding QP, while delivering average fps of 118.6, 89.2 and 49.7 for Full HD, 2160p and Ultra HD 4K sequences, respectively.

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Accelerating HEVC using heterogeneous platforms

Cited by 14 publications

References 12 publications

GPU-assisted HEVC intra decoder

GPU-assisted HEVC intra decoder

A Novel Parallel Motion Estimation Design and Implementation on GPU

Towards GPU HEVC intra decoding: Seizing fine-grain parallelism

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