Towards GPU HEVC intra decoding: Seizing fine-grain parallelism

Souza, Diego F. de; Ilić, Aleksandar; Roma, Nuno; Sousa, Leonel

doi:10.1109/icme.2015.7177515

Cited by 9 publications

(3 citation statements)

References 8 publications

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“…Regarding software-based GPU acceleration for video decoding, most of previous work targets only single HEVC decoding modules, such as Inverse Transform (IT) in [14,19], Motion Compensation (MC) in [9], Intra Prediction (IP) in [11], Deblocking Filter (DBF) in [16,25], and in-loop filters in [10]. In particular, Souza et al [13] presented a set of optimized GPU kernels, where they optimized and integrated individual HEVC modules.…”

Section: Related Workmentioning

confidence: 99%

Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU

Wang

Souza

Alvarez-Mesa³

et al. 2018

Signal Processing: Image Communication

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The High Efficiency Video Coding (HEVC) standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units (GPUs) are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of 2.2×. When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU.

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Section: Related Workmentioning

confidence: 99%

Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU

Wang

Souza

Alvarez-Mesa³

et al. 2018

Signal Processing: Image Communication

Self Cite

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“…For example, Yan et al [15] and Chi et al [16] proposed to take advantage of Single Instruction Multiple Data (SIMD) instructions for increasing HEVC decoding speed. Souza et al [17] achieved the HEVC decoding acceleration, which benefits from the parallel computing of Graphics Processing Unit (GPU). Similarly, [25] presented a new parallelization approach for accelerating HEVC decoding speed with higher arXiv:1610.02516v5 [cs.MM] 9 Jan 2018 frame rate.…”

Section: B Related Workmentioning

confidence: 99%

“…As discussed in Section III-A, we replace ∆S D (f n , w n ) and ∆S M (g n , w n ) of (21) by their normalized functions ∆ S D (f n , w n ) and ∆ S M (g n , w n ). Then, given the relationship of (14), (17), (18) and (20), formulation (21) can be finally turned to (22), where ∆C T = ∆C T − N n=1 1 N · (a · w n + b). Given the above equations, we only need to solve (22-a) when the target complexity ∆C T ≤ N n=1…”

Section: Solution To Sgcc Optimization Formulationmentioning

confidence: 99%

Saliency-Guided Complexity Control for HEVC Decoding

Yang

Wang

et al. 2018

IEEE Trans. on Broadcast.

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The latest High Efficiency Video Coding (HEVC) standard significantly improves coding efficiency over its previous video coding standards. The expense of such improvement is enormous computational complexity, from both encoding and decoding sides. Since computational capability and power capacity are diverse across portable devices, it is necessary to reduce decoding complexity to a target with tolerable quality loss, so called complexity control. This paper proposes a Saliency-Guided Complexity Control (SGCC) approach for HEVC decoding, which reduces the decoding complexity to the target with minimal perceptual quality loss. First, we establish the SGCC formulation to minimize perceptual quality loss at the constraint on reduced decoding complexity, which is achieved via disabling Deblocking Filter (DF) and simplifying Motion Compensation (MC) of some non-salient Coding Tree Units (CTUs). One important component in this formulation is the modelled relationship between decoding complexity reduction and DF disabling/MC simplification, which determines the control accuracy of our approach. Another component is the modelled relationship between quality loss and DF disabling/MC simplification, responsible for optimizing perceptual quality. By solving the SGCC formulation for a given target complexity, we can obtain the DF and MC settings of each CTU, and then decoding complexity can be reduced to the target. Finally, the experimental results validate the effectiveness of our SGCC approach, from the aspects of control performance, complexity-distortion performance, fluctuation of quality loss and subjective quality.

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