A Novel Parallel Motion Estimation Design and Implementation on GPU

Zhang, Tao; An, Xinqi; Zhao, Xin; Gao, Xinyi

doi:10.1109/access.2019.2890989

Cited by 3 publications

(4 citation statements)

References 9 publications

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“…A parallel pre-motion estimation with IME and FME was proposed by Zhang et al [23]. The efficiency of data access is achieved using a rapid mapping table algorithm.…”

Section: Related Workmentioning

confidence: 99%

Fraction Execution Resolver Using a Hybrid Multi-CPU/GPU Encoding Scheme

Papaioannou,

Koziri,

Loukopoulos

et al. 2023

Electronics

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Modern video coding standards make use of sub-pixel motion estimation to improve the video quality and reduce the bitrate. It is known that the fraction motion estimation (FME) part follows the integer motion estimation (IME) and adds an extra computational overhead due to the interpolation and the additional motion searches. In this paper, we propose a fraction execution resolver (FER) algorithm that lets the encoder skip the fraction part when specific criteria are met by introducing a preliminary fast test decision point (pFTDP) function for the IME part. If the pFTDP returns zero motion vectors (MVs) and the displacement search area center is also zero, then the fraction part is skipped. The pFTDP decision maker is executed only once, when a 2N × 2N block is first met, while all subsequent blocks follow this initial decision either by receiving the necessary MVs and RD from the pFTDP function or by using the precalculated IME values from the GPU kernel. For our experiments, we use a multithreaded CPU environment that also makes use of GPUs only for the integer part. Our evaluations provide a greater than 1600% encoding time saving at its peak in comparison with the default HEVC sequential mode and ideally a saving of greater than 2286% for still video frame sequences. The total average speedup for both Class A and Class B video sequences is ×13.45. The gain of the FER itself is more than ×3.9 compared with the same multithreaded setup environment. The PSNR and bitrate overhead observed are proportional to the tiling scheme used and are more related to the way CABAC works internally. The FER’s negative effects on coding efficiency are proven to be negligible. A balance between speed and quality achieved by using a lower tiling pattern is shown to minimize the negative effects of the encoding scheme pattern. The experimental results confirm the validity of our motivation, namely, that we can benefit from a software fraction execution resolver without any extra hardware costs. The gain is further increased when video sequences have more static blocks than others.

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“…A parallel pre-motion estimation with IME and FME was proposed by Zhang et al [23]. The efficiency of data access is achieved using a rapid mapping table algorithm.…”

Section: Related Workmentioning

confidence: 99%

Fraction Execution Resolver Using a Hybrid Multi-CPU/GPU Encoding Scheme

Papaioannou,

Koziri,

Loukopoulos

et al. 2023

Electronics

View full text Add to dashboard Cite

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“…Experiments showed that the encoding quality declined by less than 1.5%, and a 30-60× speedup was achieved compared with on single-core CPU. A parallel motion estimation implementation was proposed by Zhang et al [23], which includes pre-motion estimation, integer motion estimation, and fractional motion estimation. A rapid mapping table algorithm was introduced to improve the efficiency of data access, in addition to a quasi-integral-graph algorithm, which is designed to calculate SAD or SATD efficiently for blocks of different sizes thru GPU.…”

Section: Related Workmentioning

confidence: 99%

On Combining Wavefront and Tile Parallelism with a Novel GPU-Friendly Fast Search

et al. 2023

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As the necessity of supporting ever-increasing demands in video resolution leads to new video coding standards, the challenge of harnessing their computational overhead becomes important. Such overhead stems not only from the increased image data due to higher resolutions but also from the coding techniques per se that are introduced by each standard to improve compression. All modern standards in the field of video coding offer high compression efficiency, but this is achieved by increasing the computational complexity of the encoding part. Ultra-High-Definition (UHD) videos, bring new encoding implementation schemes that are being recommended for CPU and GPU parallelization. Therefore, several works are published to achieve better performance and reduce encoding complexity. Following this idea, we proposed and evaluated a hybrid encoding scheme that utilizes the constant growth of the CPU power with the massive GPU popularity in parallel. Taking advantage of the encoding schemes from the leading video coding standards, such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC), which support parallel processing thru Wavefront or Tiling, in our work, we combined both of them at the same time as a whole, and in addition, we introduced a GPU-friendly fast search algorithm that is highly parallel and alternative to the default non-parallel TZ-Search. Through an experimental evaluation with common test sequences, the proposed GPU Fast Motion Estimation with our previous Wavefront per Tile Parallelism (WTP) was shown to provide valid trade-off between speedup and video coding efficiency, effectively combining the best of two worlds, i.e., WTP using CPUs and parallel Motion Estimation with GPUs.

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“…Third, the paper proposes two rapid algorithms of related motion compensation: (a) one-step subpixel interpolation which eliminates the calculations of every interpolation; (b) adaptive block size motion compensation based on the accuracy of interpolation that implements motion compensation at pixel level-based block level for eliminating the interpolation number; an increase in the complexity of calculation of both encoder and decoder to the range of acceptance. Zhang et al (2019) proposed a parallel approximation method that consists of a pre-motion estimate, the entire movement estimate and the fractional movement estimate. Motion estimation is considered as the module with a relatively high computational complexity.…”

Section: Literature Review and Related Workmentioning

confidence: 99%

“…Zhang et al (2019) proposed a parallel approximation method that consists of a pre-motion estimate, the entire movement estimate and the fractional movement estimate. Motion estimation is considered as the module with a relatively high computational complexity.…”

Section: Literature Review and Related Workmentioning

confidence: 99%

An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

Balamurugan

Seshasayanan

2021

Transactions of the Institute of Measurement and Control

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Motion estimation and motion compensation techniques are effectively used for removing temporal redundancy between adjacent frames during video compression, but video quality will be degraded with the traditional pixel-based matching algorithms. To overcome this issue, diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithms are proposed in this manuscript for multi-stranded codec hardware design, which provide a high compression rate with less computational complexity. In this work, a diamond adaptive rood pattern search algorithm is used, which is a combination of a diamond-search algorithm and adaptive rood pattern search. In addition, the proposed algorithm applies multiple search strategies and terminates unnecessary searching while reserving high data regularity. The proposed diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithm for multi-stranded codec hardware design provides good performance in terms of complex calculations reduction and reaches a high speed in comparison to traditional search algorithms. The proposed architecture is implemented in Xilinx ISE design 14.5 suite and the implemented results are compared to the existing motion estimation techniques on field-programmable gate array devices. Simulation results shows that the diamond adaptive rood pattern search algorithm for multi-stranded codec hardware design provides a very good improvement in terms of computations overhead reduction, with 96.4%, 97.3% latency and 98.7% throughput and achieves a high compression rate without video quality degradation.

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A Novel Parallel Motion Estimation Design and Implementation on GPU

Cited by 3 publications

References 9 publications

Fraction Execution Resolver Using a Hybrid Multi-CPU/GPU Encoding Scheme

Fraction Execution Resolver Using a Hybrid Multi-CPU/GPU Encoding Scheme

On Combining Wavefront and Tile Parallelism with a Novel GPU-Friendly Fast Search

An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

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