Accelerating FPGA development through the automatic parallel application of standard implementation tools

Chandrasekharan, A.; Rajagopalan, Sundararaman; Subbarayan, G.; Frangieh, T.; Iskander, Yousef; Craven, Stephen; Patterson, Cameron

doi:10.1109/fpt.2010.5681754

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Server-class hardware suits the time-and memory-intensive EDA tools required to generate new FPGA configurations; these tools exceed the resources available in embedded platforms. The DMS runs the PATIS tools to accelerate hardware plug-in implementation through the automatic parallel application of standard implementation tools [13].…”

Section: Minimizing Software and Ip Trust In A Reconfigurable Plmentioning

confidence: 99%

Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement

Farag

Lerner

Patterson

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Security is difficult to achieve on general-purpose computing platforms due to their complexity, excess functionality, and resource sharing. An alternative is the creation of a Tailored Trustworthy Space for the system or application class of interest. We focus on data-intensive computing systems using reconfigurable hardware to implement streaming operations, and provide security assurances that are independent of application software, middleware, or operating system integrity and correctness. All interaction between software and the dataflow hardware passes through an automatically synthesized and formally verified hardware controller incorporating enforcement and real-time monitoring of application-specific rules. Abstractions provided by the Bluespec high-level language assist in the translation of domainspecific policy rules to synthesized logic. For the cognitive radio example used, hardware-enforced policies include physical layer rules such as sanctioned spectrum usage. Policy changes cause the secure generation and transfer of a new controller-wrapped datapath hardware plug-in. Datapath dynamic block swaps and cryptographic operations are managed entirely by the hardware controller rather than software drivers. Design for performance and design for security are therefore simultaneously addressed since the datapath is configured and monitored at hardware speeds, and software has no access to datapath configurations and cryptographic keys.

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Section: Minimizing Software and Ip Trust In A Reconfigurable Plmentioning

confidence: 99%

Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement

Farag

Lerner

Patterson

2011

2011 21st International Conference on Field Programmable Logic and Applications

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“…While developers have not widely adopted PR for production designs, the research conducted for DMD has shown that rapid development turnaround times can be achieved by partitioning frequently modified modules into separate PR regions [68]. DMD's use of PR does not extend beyond the development environment since PR regions are gradually and automatically merged out of the design.…”

Section: Dynamic Modular Design and Validationmentioning

confidence: 99%

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iskander

Patterson

Craven

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs.The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger.This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

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An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors

Khan

Kamal

Goehringer

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Accelerating FPGA development through the automatic parallel application of standard implementation tools

Cited by 3 publications

References 8 publications

Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement

Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors

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