AC Variability and Endurance Measurement Technique for Resistive Switching Memories

Deora, S.; Bersuker, G.; Matthews, K.; Gilmer, D. C.; Kirsch, P. D.

doi:10.1109/tdmr.2013.2291994

Cited by 11 publications

(15 citation statements)

References 8 publications

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“…Moreover, the random electroforming process applied to fresh devices can impose different-size initial conductive filament inside the memristor, also resulting to deviations in high and low resistance values. To model all these variability sources in memristive devices, we consider two normal distributions for the HRS and LRS values in the set of manufactured samples [8] with a defined mean and standard deviation value (Section III).…”

Section: A Process Variabilitymentioning

confidence: 99%

“…As shown in figures the PDF(g) In the following we proceed to find the probability distribution of cycles up to the second failure. By having the number of cycles at the beginning (τ) and at the point of first failure (g), we define another random variable (h), which is lifetime at cycle zero minus the time of the first failure as in (8):…”

Section: Crossbar Lifetime Analysismentioning

confidence: 99%

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Statistical lifetime analysis of memristive crossbar matrix

Pouyan¹,

Amat²,

Rubio³

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Abstract-Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.

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Section: A Process Variabilitymentioning

confidence: 99%

Section: Crossbar Lifetime Analysismentioning

confidence: 99%

Statistical lifetime analysis of memristive crossbar matrix

Pouyan¹,

Amat²,

Rubio³

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…LRS current distribution. SET pulse t rise = t fall is varied within the 10ns-1ms range and RESET pulse is kept constant (t rise = t fall =10 s) SET/RESET pulse conditions shown on top [12]. fig.…”

Section: Device and Measurement Detailsmentioning

confidence: 99%

“…11. SET pulse t rise = t fall is varied within the 10ns-1ms range and RESET pulse is kept constant (t rise = t fall =10 s) [12]. Figure 12 shows the LRS and ± LRS for different t rise /t fall of the SET pulse, as obtained from the data in figure 11.…”

Section: Device and Measurement Detailsmentioning

confidence: 99%

“…The generated oxygen ion diffuse out due to thermal and density gradient [1]. When the SET t rise /t fall is short, some oxygen ions may not have sufficient time to out-diffuse, which may lead to their recombination with the vacancies there, and, hence, higher resistivity and lower LRS current [12]. However, LRS does not chance as the underlying stochastic processes of the oxygen ions movement, controlled by temperature, field and intrinsic structural properties of the dielectric, do not expect to have strong dependency on the filament radius [12].…”

Section: Device and Measurement Detailsmentioning

confidence: 99%

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Reliability challenges in resistive switching memories technology

Deora¹

2015

2015 IEEE International Integrated Reliability Workshop (IIRW)

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In this work, the important resistive switching memory (RRAM) parameter tunability is studied in DC and AC switching mode. The tradeoff between these parameters for optimized switching are assessed. The variability in low (LRS) and high (HRS) resistance states in each consecutive pulse SET/RESET cycle is studied. It is found that HRS and LRS read current follow the log-normal and normal distributions, respectively. Endurance test from 1million switching cycles demonstrates that in a small percentage of cycles the set operation may fail, which might be missed if not all the HRS and LRS values are read. Index Terms-Low resistance state (LRS), high resistance state (HRS).2015 IIRW FINAL REPORT 7

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State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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AC Variability and Endurance Measurement Technique for Resistive Switching Memories

Cited by 11 publications

References 8 publications

Statistical lifetime analysis of memristive crossbar matrix

Statistical lifetime analysis of memristive crossbar matrix

Reliability challenges in resistive switching memories technology

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

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