AC Coupled Interconnect using Buried Bumps for Laminated Organic Packages

Wilson, John; Luo, Lei; Xu, J. Q.; Mick, S.; Erickson, Evan; Su, Hsuan-Jung; Chan, Bor-Wen; Lin, How; Franzon, Paul D.

doi:10.1109/ectc.2006.1645624

Cited by 6 publications

(5 citation statements)

References 6 publications

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“…Using a MCM-L, as an interposer between an ACCI chip and PCB, would enable this technology to interface and communicate across cards or in backplane applications. The capacitive interface would be created between the chip and the MCM-L, and a different arrangement for the solder bumps is preferred given the coefficient of thermal expansion (CTE) mismatch between the chip and MCM-L [13].…”

Section: Transmission Line Design Issues With Acci Using Buried Bmentioning

confidence: 99%

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Wilson

Mick

et al. 2007

IEEE Trans. Adv. Packag.

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Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10 12 , across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35-m complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.Index Terms-AC coupled interconnect (ACCI), buried bumps, capacitive coupling, MCM, pulse signaling, noncontacting I/O, chip and package co-design.

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Section: Transmission Line Design Issues With Acci Using Buried Bmentioning

confidence: 99%

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Wilson

Mick

et al. 2007

IEEE Trans. Adv. Packag.

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“…It does not have the constraints on dynamic range of the output swing nor the need of a common-mode feedback circuit. This MultiCap scheme is readily compatible with traditional ACCI signaling system [1]. And it inherits the advantages of ACCI, including high I/O density, potential to improved yield, and increased long-term reliability.…”

Section: Multicap As σ Blockmentioning

confidence: 99%

“…For example, given a set of variables; A pad = 175x175µm 2 (200µm pitch and 25µm spacing on package from [1]), C C,row,min = 500fF (from preliminary simulation with TRX in 0.13µm standard CMOS and 80cm microstrip on FR4 PCB), d = 1µm (assumed), k = 18 (from [7]), N tap = 4, and R = 3, substituting into (5) …”

Section: A Parameter Analysis Of the Multicap Structurementioning

confidence: 99%

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A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE

Pitts

Franzon

et al. 2010

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

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Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block of the transmit FFE and has zero power consumption. A set of equations are derived to estimate the useable value of the MultiCap, of which the range is bounded by I/O pitch, receiver sensitivity, and other parameters. The parasitics of this device are proven to be negligible. Simulation in 0.13µm standard CMOS process shows that the MultiCap structure could enable a power saving of more than 90% over the conventional current-mode FFE.

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“…Alternatively, the same goal can be achieved by decreasing the dielectric thickness, decreasing the circuit complexity (such as lower N tap ), or improving the RX sensitivity (hence lowering C C,row,min ). Take the same example used in (6), if all the parameters are fixed except for k,…”

Section: A CCmentioning

confidence: 99%

AC Coupled Interconnect for Low Power Spaceborne Electronics

Franzon¹,

Lipa²

2012

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AC Coupled Interconnect using Buried Bumps for Laminated Organic Packages

Cited by 6 publications

References 6 publications

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Fully Integrated AC Coupled Interconnect Using Buried Bumps

A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE

AC Coupled Interconnect for Low Power Spaceborne Electronics

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