A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE

Abstract

Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block of the transmit FFE and has zero power consumption. A set of equations are derived to estimate the useable value of the MultiCap, of which the range is bounded by I/O pitch, receiver sensitivity, and other parameters. The parasitics of this device are proven to be negligible. Simulation in 0.13µm standard CMOS process shows that the MultiCap structure could enable a power saving of more than 90% over the conventional current-mode FFE.