A 0.65 mW/Gbps 30 Gbps capacitive coupled 10 mm serial link in 2.5D silicon interposer

Karim, M. A.; Franzon, Paul D.

doi:10.1109/epeps.2014.7103614

Cited by 6 publications

(2 citation statements)

References 9 publications

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“…Silicon die size directly links to the manufacturing cost. Therefore, the area efficiency is one of the important design factors of the DRAM [4]. To achieve low operation energy, we need to re-consider DRAM structure.…”

Section: Simd Tilementioning

confidence: 99%

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3D-enabled customizable embedded computer (3DECC)

Franzon

Rotenberg

Tuck

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for "embedded applications" like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today's CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows.

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Section: Simd Tilementioning

confidence: 99%

“…The general architecture of the SIMD stack is shown in Figure 2 and for the interposer system in Figure 3. Low power pulse signaling was used on the interposer so as to minimize interconnect power at 0.69 pJ/bit [4]. …”

Section: 5d and 3d Designmentioning

confidence: 99%