Abnormal Relationship Between Hot Carrier Stress Degradation and Body Current in High-k Metal Gate in the 14-nm Node

Chang, Kai‐Chun; Liao, Jih-Chien; Chang, Ting‐Chang; Yeh, Chien‐Hung; Lin, Chih-Yang; Jin, Fu‐Yuan; Lin, Yu‐Shan; Ciou, Fong‐Min; Hung, Wei‐Chun; Lin, Yen-Sheng; Lien, Chenhsin; Cheng, Osbert; Huang, Chihpin; Ye, Yi-Han

doi:10.1109/led.2019.2899630

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…Hence, both the LEM and SVE mechanisms describe the reaction of a single high energy electron, while EES and MVE describe more than one reacting electron. Not only do planar MOSFETs follow this trend, but it is also found in the FinFET structure, as our team has demonstrated [8].…”

Section: Resultsmentioning

confidence: 61%

“…Some previous [15,16] have noted the lucky electron model (LEM), which is related to the transverse electric field. However, as the channel length scales down, both Guerin's and our teams have reported in 2007,2009 and 2019 that the mechanisms under HCS are in fact not LEM, but rather single vibrational excitation (SVE), electronelectron scattering (EES), and multiple vibrational excitation (MVE) [8,[17][18][19][20]. With the transformation of the HCS mechanisms, therefore, the prediction of HCD needs to be revised.…”

Section: Introductionmentioning

confidence: 99%

“…Moore's Law [3][4][5]. FinFETs [6][7][8] have been proposed as a method to replace traditional planar transistors [9]. Due to the conventional process, the profiles of fins tend to be trapezoidal or triangular [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

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Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node

Kuo¹,

Chen²,

Chang³

et al. 2022

Semicond. Sci. Technol.

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This study investigates the impact of fin profiles under hot carrier stress, which defines different base widths: wide-base samples with the smallest slope, medium-base samples, and narrow-base samples with a larger slope. The performance of the narrow samples is better than the medium samples, regardless of transconductance, on-state current, subthreshold swing or drain-induced barrier lowering, demonstrating that the narrow profile samples’ mobility and gate control are better. In long channel devices, the trend of hot carrier degradation (HCD) is in agreement with previous references, and is dependent on the transverse electric field and the fin shapes. However, this trend does not exist for short-channel devices. Positive bias stress and technology computer aided design simulation are applied for investigation and to clarify the reasons for this abnormal HCD trend. Finally, by fitting the multiple vibrational excitation (MVE) mechanism, the slope of the trend lines in the short channel devices are found to indeed match the bending mode. In other words, the disappearance of the general trend between the HCD and fin profiles is caused by the change in the mechanism in the short-channel device. Because the MVE mechanism is independent from the electric field, the narrow profile fin shape more effectively promotes gate control and better performance without affecting the reliability in short channel devices. These results can provide a clear direction for fin shape designers in the future.

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Section: Resultsmentioning

confidence: 61%

Section: Introductionmentioning

confidence: 99%

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Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node

Kuo¹,

Chen²,

Chang³

et al. 2022

Semicond. Sci. Technol.

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“…Recently, this 3-energy lifetime modelling has been applied to (3D) FinFETs [31], [32] , leading to successful modelling of HCD taking into account impact of series resistance and self-heating effects [32] .…”

Section: A Hot-carrier Damage Using Msm Techniquementioning

confidence: 99%

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

Bravaix,

Hamparsoumian,

Sonzogni

et al. 2023

J. Phys.: Conf. Ser.

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The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

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Applied Engineering on Physics‐of‐Healthy and SHM of Microelectronic Equipment for Aeronautic, Space, Automotive and Transport Operations

2022

Reliability and Physics‐of‐Healthy in Mechatronics

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Abnormal Relationship Between Hot Carrier Stress Degradation and Body Current in High-k Metal Gate in the 14-nm Node

Cited by 5 publications

References 10 publications

Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node

Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

Applied Engineering on Physics‐of‐Healthy and SHM of Microelectronic Equipment for Aeronautic, Space, Automotive and Transport Operations

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