This work investigates the effect of process temperature on one-transistor-one-capacitor ferroelectric random access memory (1T1C FeRAM) cells fabricated with a HfZrOx ultrathin film applied as the 1T1C capacitor. Traditionally, the capacitor in 1T1C devices is grown on the drain, and such a structure is a type of dynamic memory. Such a structure, however, is prone to the leakage current phenomenon, which causes the amount of charge stored in the capacitor to be insufficient, leading to inaccurate data reading. To solve this problem, an alternative 1T1C structure placing the capacitor on the gate terminal has been proposed. For these alternative 1T1C FeRAM devices, our experimental results indicate that the deposition temperature of the ferroelectric layer has a significant effect on the basic electrical properties. To clarify this phenomenon, we propose a physical model which is based on the effect of the deposition temperature on the HfZrOx grain size.
A scanning tunneling microscope (STM) was used for the first time to investigate the (100)CoGa/GaAs interfaces grown by molecular beam epitaxy. The surface image indicates a vertical variation of about 7.5 Å with some domains of dimensions of about 170 Å. Furthermore, ballistic-electron-emission-microscopy spectra of this metal/semiconductor interface show two turn-on voltages, which account for the change of transmission probabilities for electrons with energies above the L minima and X minima of GaAs, respectively. The transmission into the X valleys of GaAs is found to be relatively stronger than that into the L valleys. This is explained by the CoGa band structure and the conservation of energy and transverse momentum for ballistically injected electrons. So far no ballistic electron current flowing into the Γ valley has been observed. For this reason, Schottky barrier height and its spatial variation measured by STM were not directly from the anticipated turn-on voltage at the Γ minimum, but instead, from the thresholds corresponding to transmission into higher valleys.
This work performs fundamental electrical measurements and a positive bias temperature instability (PBTI) test on an N-type metal oxide semiconductor capacitor (MOSCAP) and a La 2 O 3 dipole-doped N-type MOSCAP. Experimental results show that the dipole-doped N-type MOSCAP has a lower threshold voltage and gate current leakage than do the N-type MOSCAP. After positive bias stress, an abnormal gate current leakage decrease appears in both dipole-doped and normal N-type MOSCAPs under short term stress. Analysis of capacitance and gate current measurements indicate that electron trapping and defect generation cause the change in gate current after positive bias stress. Generally, devices with higher gate leakage have more severe degradation after PBTI. However, in this work, the dipole sample shows a lower initial gate current leakage but higher gate current degradation than those found in the control sample after PBTI. Based on the electrical measurement results and the energy band simulation, a conduction model was proposed to explain the abnormal PBTI of the dipole-doped N-type MOSCAP.
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