A WLAN and bluetooth combo transceiver with integrated WLAN power amplifier, transmit-receive switch and WLAN/bluetooth shared low noise amplifier

Winoto, Renaldi; He, Mi; Lu, Yuan; Signoff, David; Chan, Eliza; Lin, Chi‐Hung; Loeb, Wayne; Park, Jinho; Lin, Li

doi:10.1109/rfic.2012.6242307

Cited by 9 publications

(3 citation statements)

References 4 publications

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“…It is also applied for both coordinate rotation digital computer (CORDIC) design [17] and QR decomposition [18] in multiple-input multiple-output (MIMO) applications. Even for a small building-block of a low noise amplifier (LNA), the reused-hardware technique is still considered in [19]. As a result, no matter how small a building-block is, the hardwareefficiency is an important design consideration in chip design.…”

Section: B Motivationmentioning

confidence: 99%

VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications

2015

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Dedicated short-range communication (DSRC) plays an important role in sensor networking for intelligent transportation system (ITS) applications. How to achieve a higher hardware-efficiency becomes an attractive issue to design each critical building-bock in sensor node. DSRC standards usually adopt either FM0 code or Manchester code as a coding technique to enhance signal reliability. In this paper, a fully-reused VLSI architecture of FM0/Manchester codec with a hardware utilization rate (HUR) of 100% is proposed for DSRC-based sensor node. It is based on the half-cycle processing model (HCPM). The HCPM includes three core techniques: half-cycle logic partition (HCLP), reused-based retiming (RBR), and Boolean function reshaping (BFR). The HCPM can improve the HUR of FM0/Manchester codec from 27.33% to 100% with the reduction of the transistor count from 86 to 66. A 100% HUR means every transistor is activated; therefore, a more power is consumed. With a design trade-off between HUR and power consumption, this work still presents a higher energy-efficiency. This work is realized in TSMC 0.18 um 1P6M CMOS technology. The silicon area of core circuit is 33 × 120 um 2 . The experiment results demonstrate that this work presents a competitive performance with 100% HUR compared with existing works. With this work, DSRCbased sensor nodes can present a 100% HUR FM0/Manchester codec, fully supporting DSRC standards of Europe, USA, and Japan.

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Section: B Motivationmentioning

confidence: 99%

VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications

2015

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“…Antenna-filter-switch-PA or LNA sequence is preferred as the most general circuit form for communication protocols. Along with WLAN, another communication technology such as Bluetooth can be used in this system by adding new switches [1]. Low noise figure and high linearity are important figures of merits for designing an LNA [2] which can also be used for Worldwide Interoperability for Microwave Access (WiMAX) apps [3][4].…”

Section: Introductionmentioning

confidence: 99%

Power Amplifier and Low Noise Amplifier for WLAN Applications

Duman

2022

ECJSE

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WLAN applications operating at a frequency of 2.45 GHz are a frequently used communication method in transmission tools. The connection functions to send and receive data between access points and smart devices are also fulfilled by WLAN technology. Communication quality in data transfer gains importance for this technology at every stage. Front-end module structures are used to increase such quality affects directly the efficiency. Circuits including power amplifier (PA), low noise amplifier (LNA), antenna and filter are the most significant components compose front-end structures. In this study, PA and LNA using PW570 gain block & BFP760 RF transistor circuit respectively are proposed. By means of the usage of the proposed circuits, there will be considerable improvements in data communication speed and area of coverage, which are among the WLAN performance factors.

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“…Although a switch-mode PA theoretically has 100% of the drain efficiency, it cannot be directly applicable to the modulation scheme, which utilizes the amplitude of the transmitting signal. To overcome this issue, a polar power amplifier has been introduced using a mixed-signal technique [3]. However, the size of the mixed-signal, 2.4 GHz PA is bulky (3.06 mm 2 ), due to the extra RF digital-to-analog converter for the polar operation.…”

Section: Introductionmentioning

confidence: 99%

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

2019

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We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

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A WLAN and bluetooth combo transceiver with integrated WLAN power amplifier, transmit-receive switch and WLAN/bluetooth shared low noise amplifier

Cited by 9 publications

References 4 publications

VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications

VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications

Power Amplifier and Low Noise Amplifier for WLAN Applications

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

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