A Wideband Inductorless Single-to-Differential LNA in &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$0.18 \mu{\rm m}$&lt;/tex&gt; &lt;/formula&gt; CMOS Technology for Digital TV Receivers

This article presents a new transistor size rule for a resistive‐feedback inverter implemented as a low‐noise amplifier (LNA) for wideband applications. To enhance the noise figure (NF) and voltage gain (Av), the inverter LNA requires large transconductance (Gm), resulting in large current consumption (ID). The proposed large‐NMOS inverter‐LNA obtains a better power efficiency (Gm/ID) with a smaller transistor compared with the conventional large‐PMOS structure. Because there are trade‐off relationships between NF, Av, 3‐dB bandwidth, and power dissipation in the inverter‐LNA design, a figure‐of‐merit (FOM) including all of these parameters is maximized by varying the transistor size obtained from the graphical optimization. Thus, the proposed new size ratio rule achieves superior LNA performances compared to the conventional rule, as demonstrated by the theoretical analysis, simulation, optimization, and measurement. Measurements show a maximum power gain of 16.8 dB, a minimum NF of 1.84 dB, and a maximum third‐order input intercept point of −9.4 dBm over 0.05 to 1.4 GHz while the LNA consumes 9.6 mW from a 1.5 V supply. The proposed LNA is implemented using a Samsung 65‐nm RF CMOS process.

Section: Me As Ur Eme Nt Re S Ultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analysis and optimization of a resistive‐feedback inverter LNA

Park

Lee

Yeo

et al. 2018

Low‐power inductorless wideband SFBB balun low noise amplifier with noise reduction and third‐order transconductance optimization

Tiwari

Mukherjee

2020

This article presents an inductorless wideband balun low noise amplifier (LNA), which uses noise reduction and linearity optimization techniques at low supply voltages. The proposed self forward body biased LNA uses inverter type amplifier structure as input stage for impedance matching while output stages are noise reduction stages, which partially cancel the noise of the input stage. In addition to noise reduction, transistors are biased nearzero third-order transconductance region to maximize third-order input-referred intercept point (IIP3) performance at low supply voltages. The LNA, implemented in 180 nm RFCMOS technology, is evaluated at 1 and 0.9 V supply voltages to show low voltage operation. It shows a maximum voltage gain of 19.7 dB with a minimum noise figure of 2.7 dB and a maximum 3-dB bandwidth that spans from 300 MHz to 1.83 GHz. The minimum achieved IIP3 at 0.9 V supply voltage is −1.7 dBm. The circuit draws a maximum current of 10.36 mA from 1 V power supply and occupies an area of 0.08 mm 2 .

A wideband CMOS LNA using noise‐canceling topology and g_m‐boosting technique

Zheng

Feng

Chen

et al. 2023

In this letter, a wideband low noise amplifier (LNA) using noise‐canceling topology and gm‐boosting technique is proposed. The noise‐canceling topology is used in the common gate (CG) amplifier to achieved better noise figure (NF) and wideband input matching. Meanwhile, the requirement of the input transconductance can be obviously decreased due to the application of gm‐boosting technique, which effectively alleviate the trade‐off between power consumption and voltage gain. The 3‐dB bandwidth of the LNA is from 2.1 to 4.1 GHz, covering widely used 5 G wireless communication frequency bands (n1, n7, n38, n41, n66, and n78 bands). The proposed LNA shows a flat and low measured NF of 3.3–3.6 dB within the operating bandwidth, while the peak power gain is 18.7 dB. The power consumption of this circuit is 16 mW with 1.2 V supply voltage, and the core area of the circuit is 0.066 mm2 with only one inductor for the whole chip.