Low‐power inductorless wideband <scp>SFBB</scp> balun low noise amplifier with noise reduction and third‐order transconductance optimization

Tiwari, Shashank; Mukherjee, Jayanta

doi:10.1002/mop.32545

“…Nevertheless, their FOM is inferior to the proposed LNA due to their high power dissipation. Although better IIP3 is achieved by Yu et al 24 and Tiwari and Mukherjee, 41 this improvement has been performed by consuming more power. In Kim and Kwon, 27 Tiwari and Mukherjee, 41 and Joo et al, 42 a buffer is needed to obtain output impedance matching, resulting in increased dissipated power and the die area.…”

Section: Simulation Resultsmentioning

confidence: 98%

“…Although better IIP3 is achieved by Yu et al 24 and Tiwari and Mukherjee, 41 this improvement has been performed by consuming more power. In Kim and Kwon, 27 Tiwari and Mukherjee, 41 and Joo et al, 42 a buffer is needed to obtain output impedance matching, resulting in increased dissipated power and the die area. In contrast, the recommended LNA inherently provides output impedance matching without the demand for any extra circuit.…”

Section: Simulation Resultsmentioning

confidence: 98%

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A low‐power wideband LNA exploiting current‐reuse and noise cancelation techniques

Khanehbeygi

¹

,

Jafarnejad

²

,

Koozehkanani

³

et al. 2022

Circuit Theory & Apps

0

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This paper presents an inductorless low-power wideband Low Noise Amplifier (LNA) in TSMC 0.18 μm CMOS technology. The proposed LNA is based on the Common-Gate (CG) topology, which consists of three consecutive stages: CG, Common-Source (CS), and Collector stage. The CG and CS configurations are responsible for providing the wideband input impedance matching and the majority of the gain, respectively. The overall performance of the LNA has been improved by applying noise cancelation, capacitive-peaking, and current reuse techniques. Unlike the conventional structure, the CG and CS sections' noise is canceled by utilizing a novel noise-canceling mechanism, simultaneously. Furthermore, with the capacitive-peaking technique, the voltage gain drop across hi gher frequencies is prevented, and thus, the bandwidth of the structure is improved. The trade-off between power consumption and input impedance has been dramatically resolved by employing the current reuse technique in the CG stage. Post-layout simulation results of the presented noise-canceling LNA demonstrate a Noise Figure (NF) of 2.19-2.58 dB and a maximum voltage gain of 19.84 dB with a À3 dB bandwidth of 0.2-2.85GHz. The simulated input/output matching (i.e., S11/S22) is better than À14.73/À19.43 dB in the entire bandwidth. Additionally, Input Third Intercept Point (IIP3) of À4.56 dBm is achieved. The results are gained by consuming only 2.87 mW under a supply voltage of 1.2 V and occupying a 0.0429 mm 2 of die area.

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“…Recently many complementary nMOS-pMOS based low power balun LNAs are proposed [20]- [23]. While design in [21] has limited linearity improvement, designs in [20], [22] have poor linearity performance. The design in [23] proposes linearity improvement while using external inductor.…”

Section: Background In Balun Lna Designsmentioning

confidence: 99%

An Inductorless Low Power Wideband Push-Pull Balun LNA with Dual Stage Noise Cancelation andIIP2/IIP3 Linearity Modes for Sub-GHz Wireless Applications

Tiwari¹,

Mukherjee²

2022

Preprint

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1

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<p>In this paper, an inductorless common source (CS) - common gate (CG) complementary push-pull balun LNA is proposed for sub-GHz low power applications. A dual stage noise cancelation technique is proposed to reduce the noise figure (NF) of the circuit. To maximize the linearity performance, a tunable nMOS based source follower feedback in shunt to the CS stage is employed. Tunable feedback maximizes the IIP2 in the IIP2 mode while it maximizes the IIP3 in the IIP3 mode. The circuit operates in two power modes - low power mode (LPM) (1.2 V supply) and high linearity mode (HLM) (1.8 V supply). In the LPM , IIP2 performance is improved while IIP3 performance is limited by the third order output conductance non-linearity. In the HLM, both IIP2 and IIP3 performance is maximized. The circuit, implemented in 0.18µm RFCMOS process, achieves a maximum gain of 15.5 dB with minimum NF of 3.2 dB while maximum 3-dB bandwidth ranges from 65 MHz to 840 MHz. In the LPM, the maximum IIP2 and the maximum IIP3 are 48 dBm and 1.3 dBm respectively while in the HLM, the maximum IIP2 and the maximum IIP3 are 43 dBm and 8.3 dBm respectively. In LPM, it dissipates a maximum total power of 3.75 mW while in the HLM, it dissipates a maximum total power of 6.4 mW. To the authors’ best knowledge, the proposed balun LNA achieves the best linearity performance reported till date.</p>

show abstract

“…Recently many complementary nMOS-pMOS based low power balun LNAs are proposed [20]- [23]. While design in [21] has limited linearity improvement, designs in [20], [22] have poor linearity performance. The design in [23] proposes linearity improvement while using external inductor.…”

Section: Background In Balun Lna Designsmentioning

confidence: 99%

An Inductorless Low Power Wideband Push-Pull Balun LNA with Dual Stage Noise Cancelation andIIP2/IIP3 Linearity Modes for Sub-GHz Wireless Applications

Tiwari¹,

Mukherjee²

2022

Preprint

Self Cite

1

0

View full text Add to dashboard Cite

<p>In this paper, an inductorless common source (CS) - common gate (CG) complementary push-pull balun LNA is proposed for sub-GHz low power applications. A dual stage noise cancelation technique is proposed to reduce the noise figure (NF) of the circuit. To maximize the linearity performance, a tunable nMOS based source follower feedback in shunt to the CS stage is employed. Tunable feedback maximizes the IIP2 in the IIP2 mode while it maximizes the IIP3 in the IIP3 mode. The circuit operates in two power modes - low power mode (LPM) (1.2 V supply) and high linearity mode (HLM) (1.8 V supply). In the LPM , IIP2 performance is improved while IIP3 performance is limited by the third order output conductance non-linearity. In the HLM, both IIP2 and IIP3 performance is maximized. The circuit, implemented in 0.18µm RFCMOS process, achieves a maximum gain of 15.5 dB with minimum NF of 3.2 dB while maximum 3-dB bandwidth ranges from 65 MHz to 840 MHz. In the LPM, the maximum IIP2 and the maximum IIP3 are 48 dBm and 1.3 dBm respectively while in the HLM, the maximum IIP2 and the maximum IIP3 are 43 dBm and 8.3 dBm respectively. In LPM, it dissipates a maximum total power of 3.75 mW while in the HLM, it dissipates a maximum total power of 6.4 mW. To the authors’ best knowledge, the proposed balun LNA achieves the best linearity performance reported till date.</p>

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Low‐power inductorless wideband SFBB balun low noise amplifier with noise reduction and third‐order transconductance optimization

Cited by 4 publications

References 8 publications

A low‐power wideband LNA exploiting current‐reuse and noise cancelation techniques

A low‐power wideband LNA exploiting current‐reuse and noise cancelation techniques

An Inductorless Low Power Wideband Push-Pull Balun LNA with Dual Stage Noise Cancelation andIIP2/IIP3 Linearity Modes for Sub-GHz Wireless Applications

An Inductorless Low Power Wideband Push-Pull Balun LNA with Dual Stage Noise Cancelation andIIP2/IIP3 Linearity Modes for Sub-GHz Wireless Applications

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