A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

Lü, Jian–Qiang; Kwon, Yongchai; Rajagopalan, G.; Gupta, Manish; McMahon, Jeffrey M.; Lee, K.-W.; Kraft, R.P.; McDonald, J. F.; Cale, Timothy S.; Gutmann, R.J.; Bai, Xu; Eisenbraun, Eric; Castracane, James; Kaloyeros, A. E.

doi:10.1109/iitc.2002.1014893

Cited by 18 publications

(14 citation statements)

References 7 publications

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“…Although it is possible to bond at the wafer level, this approach is most suitable for die-level bonding (using a flip-chip bonder). At the right the figure illustrates 3D stacking based on thin-film bonding (metal-metal or dielectricdielectric) [19,20,21]. Not only are solder bumps eliminated in this approach, but also increased interconnect density and tighter alignment accuracy may be achieved when compared to the previous approach due to the fact that these approaches are based on wafer-scale bonding (although there are challenges in aligning 12-inch wafers, for example).…”

Section: Evolution Of Conventional Silicon Ancillary Technologies: a mentioning

confidence: 95%

Power delivery, signaling and cooling for 2D and 3D integrated systems

Bakir

Huang

Dang

2010

Integrated Circuits and Systems

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Section: Evolution Of Conventional Silicon Ancillary Technologies: a mentioning

confidence: 95%

Power delivery, signaling and cooling for 2D and 3D integrated systems

Bakir

Huang

Dang

2010

Integrated Circuits and Systems

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“…Therefore, we model the D2D interconnect as a 10μm (20μm) length of top-level metal for the face-to-face (backside) vias. This is a conservative assumption as previous work has indicated that the entire height of a thinned die can be less than 10μm [29]. To optimize our scheduler designs, we sweep through a range of transistor sizes and use the transistor sizes that minimize the overall scheduler delay.…”

Section: Circuit Latency and Energy Es-timationmentioning

confidence: 99%

Dynamic instruction schedulers in a 3-dimensional integration technology

Puttaswamy

Loh

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the critical path latency of a conventional dynamic scheduler is greatly affected by wire delay, we propose 3D-integrated scheduler designs by partitioning a conventional scheduler across multiple vertically-stacked die. The die-stacked organization reduces the lengths of critical wires thus reducing both latency and energy. Our simulation results show that a 20-entry (60-entry) instruction scheduler implemented in a 2-die stack achieves a 9% (15%) reduction in latency with simultaneous energy reduction as compared to a conventional planar design. The benefits are even larger when the instruction scheduler is implemented on a 4-die stack, with the corresponding latency reductions being 12% (22%).

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“…A schematic of a technology platform for wafer-level 3D shows heterogeneous integration of systems. Monolithic wafer alignment, bonding, thinning, and inter-wafer interconnection are unit steps [4][5].…”

Section: Introductionmentioning

confidence: 99%

Surface Energy Characterization of Partially Cured Benzocyclobutene for 3D Interconnect Applications

2007

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Accommodation of nonplanarity is required in a monolithic waferlevel three-dimensional (3D) technology platform, in which two damascene patterned copper/benzocyclybutene (BCB) layers are bonded to form mechanical bonds between wafers and inter-wafer copper interconnects. The temperature dependence of the surface energy of partially-cured BCB, an important material parameter for determining accommodation of nonplanarities, is characterized using contact angle measurements and varies in the range of 39-50 mJ/m 2 between 35 o C and 230 o C. These changes are discussed with respect to the surface structure and mechanical properties of the BCB, and should not be a barrier to usage of partially-cured BCB as a bonding material.

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A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

Cited by 18 publications

References 7 publications

Power delivery, signaling and cooling for 2D and 3D integrated systems

Power delivery, signaling and cooling for 2D and 3D integrated systems

Dynamic instruction schedulers in a 3-dimensional integration technology

Surface Energy Characterization of Partially Cured Benzocyclobutene for 3D Interconnect Applications

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