A Wafer Level approach for led packaging using TSV last technology

Volpert, M.; Soulier, Brigitte; Borel, S.; Ait-Mani, N.; Gaugiran, S.; Gasse, A.; Henry, David D.

doi:10.1109/ectc.2015.7159732

Cited by 3 publications

(1 citation statement)

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“…Through silicon via (TSV) technology has become attractive as a potential solution to further extend Moore's law through vertical connection to realize boosts in system performance and integration density while maintaining acceptable fabrication costs using wafer-level packaging [5]. Various studies have shown the process readiness of 2.5D Si interposer [6][7][8] or embedded TSV as wide I/O [9], although low-volume TSV technology is from via-last wafer-level packaging, which uses TSV with partial metal filling [10,11]. Although this is a more cost-effective wafer-level packaging solution, it is not suitable for implementation in applications such as sensors, RF, and power devices that require good signal quality, robust reliability, and acceptable fabrication costs under squeezed package sizes (both for planar format and vertical thickness).…”

Section: Introductionmentioning

confidence: 99%

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

et al. 2021

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Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

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