A VLSI sequencer chip for ATM traffic shaper and queue manager

Abstract

H. Jonathan Chao and Necdet UzunBellcore and Polytechnic University? is required to effectively and fairly allocate the shared The asynchronous transfer mode (ATM) technique provides a standardized and flexible scheme to transport and switch traffic effectively for different services. To provide satisfactory quality of service (QOS) to all users on the network, it is necessary to control the users' traffic so that network resources, such as transmission bandwidth and buffer capacity, can be efficiently and fairly utilized by all the users while still meeting the individual QOS requirement. However, due to the natural randomness of the broadband traffic (e.g., data file transfer and variable bit-rate video communication), it is difficult to control users' traffic effectively so that network congestion is prevented or, at least, occurs rarely. In this paper, we propose to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface ("1) by a queue manager. The traffic enforcer adopted in our work contains a buffer to delay and reshape the violating cells that do not comply with some agreed-upon traffic parameters, and thus is also called a traffic shaper. The queue manager manages the queued cells in network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. We present in the paper our proposed architectures for the traffic shaper and the queue manager. We have implemented and tested a key component, called the Sequencer chip, to realize both architectures. The Sequencer chip is implemented using 1 . 2 -~m CMOS technology. It contains about 150k transistors, has a die size of 7.5 mm x 8.3 mm, and is packaged in a 223-pin ceramic pin grid array P G A ) carrier.

A traffic shaper for supporting CBR and VBR services in ATM networks

“…In order to implement the proposed traffic shaper, the queued cells in the EDD schedulers must be sorted according to their due-dates. According to [14,15], this requires a search or sort operation whenever a new cell enters the scheduler. Since the due-dates vary with time and may complicate the implementation of EDD scheduler, the deadline DL j (k), which is a constant and defined as DL j (k) = ET j (k) + IDD j (k), can replace the due-date as the sorting metric.…”

“…In addition, a modification to the simple EDD algorithm in [14] or [15] is required due to the addition of the feedback control mechanism. The modification is simply described as follows.…”

Design of packet-fair queuing schedulers using a RAM-based searching engine

“…1) Design Issue I: Instead of using the sorting approach to find the smallest time stamp, where the time complexity can be for binary sorting or for parallel sorting [35], we use the search-based approach to reduce implementation complexity. In the search-based approach, time stamps are quantized into integers and are used as the address for the priority queue.…”

“…But its time complexity is high for large , and it is expensive to implement. An application-specific integrated circuit (ASIC) called a sequencer chip [35] was used to facilitate the priority queue with a time complexity of , independent of the number of sessions in the system. However, each sequencer chip can only handle up to 256 sessions.…”

Fast and scalable priority queue architecture for high-speed network switches

“…In the literature, several hardware-based sorted priority queue architectures have been proposed: calendar queues [1], binary-tree-of-comparators-based priority queues [21], [22], shift-register-based priority queues [2], [3], [23], and systolicarray-based priority queues [14], [15], [17]. All of these schemes have one or more shortcomings.…”